Digital Step Attenuator Investigation

Several steps were taken to understand the 4.7MHz impulses on the digital step attenuator (channel 1).

First, additional supply bypass capacitance values were used.  Smaller values were added in parallel and larger values switched in.  These steps had minimal effect on the impulses.

Second, the QFN pad ground contact was revisited by trying to flow solder into the via under the device.  This is a tricky action as it is difficult to get good thermal distribution from the bottom with such a small via.  The solder mask is tight around it on the bottom which disallows the initial formation of a solder blob/bubble.  In addition, I do not have a good way of warming the part itself from the other side properly.  The best technique I have found is to stick a small resistor lead wire into the via, tilt it to make contact with the via sides, allow it to transfer heat down the via and onto the pad, then apply solder and let it wick along the lead.  I'm not entirely sure about the success, however, the via did fill with solder and should have made good contact with some of the QFN pad.   Unfortunately, this makes no difference in the attenuator impulse noise.

Third, in an effort to understand if there is some kind of interaction between the attenuator and the switch (recall none of the other channels produce such impulse noise) various permutations of input port selection with output port selection were attempted with the input and output ports monitored (i.e. set the input RF mux to enter the attenuator but configure the output mux to select channel 0, set the input RF mux to select channel 0 while the output mux selects the attenuator, ...).  In the end, even with no mux ports configured to the attenuation channel, the impulse noise is only present when the attenuator powered on.

Finally, on review of the datasheets for follow on parts to the one used, recommendations on not powering up in parallel mode were noted.  This is in an effort to establish proper internal voltage values with ~400uS required from power up until latch enable (LE) for the parallel attenuation value.  The design for the R board used the parallel interface for simplicity and provides a power enable to quiet each of the 4 channels while not in use.  Unfortunately, as layed out LE is not individually controllable.  To investigate this, the board was modified by cutting the LE trace to the attenuator, connecting it to one of the spare GPIO lines (W0 to the unused channel 0), and corresponding software updates made.  (trying to get a white wire on a pulled out pad which is 0.5mm pitch from others is an exercise in patience).  Those changes, with the accompanying attenuator channel results are shown below with a 400MHz input.

In short, the 4.7MHz impulses are still present (and now I have a cut up board ;-).  As a last ditch effort to ensure proper QFN pad grounding and eliminate any one-off issues on this particular board I'll construct a second unit.

R Board Results

Each of the channels on the board was briefly investigated.

Channel 0

Channel 0 was selected with no carrier module.  This provides a basic sanity check on the input/output muxes and board noise environment.  The following is a 0-1000MHz sweep of the R board output with no input and channel 0 selected.

The small signals at ~-80dBm in the 300MHz - 400MHz are expected local environmental noise.

Channel 1

Channel 1 had a -30dBm 100MHz square wave input signal with the following results (0-1000MHz sweep).

The signal attenuation is as expected, however, the noise hump was not expected.  The noise is actually a set of 4.7MHz harmonics (shown below centered on 100MHz).  These are independent of the input signal (level and frequency) and present with no input.  This is unique to this channel (more later).

Channel 2

Channel 2 was initially populated as a 150MHz common base amplifier using the following components.

Component	Value	Function
C114	DNI	CC Input Bypass
C103	1nF	CB Input Bypass
C116	DNI	CC RF ground
C126	1nF	CB RF ground
R106	2.2k	Bias upper
R107	2.2k	Bias lower
R105	33	Collector current control
L104	1uH	Output tune
C115	10pF	Output tune

This was anticipated to produce no more than 17dB of gain.  Large signal gain measurements (i.e. -30dBm input) show power gains dropping to -9dB as expected and centered slightly above 150MHz (following figure).

The output of this channel was used with an A-B stack as a one stage SDR receiver on the local weather service narrow band FM channel at 162.45MHz.  The following captures those results - left is channel 0 at 0dB attenuation, right is channel 2 selected. The level difference is 15dBm which aligns nicely with expected results.  

Channel 3

The amplifier used in channel 3 is an AD8352 with a 3.3V supply.  The following is from the datasheet.

Channel 3 gain was evaluated by using a -30dBm source and the 7L12.  Since the source is home made and the 7L12 hasn't been professionally calibrated in a very long time, the overall error is at least 1 dB.  The following figure captures the measured gain to 1800MHz (7L12 limit).

We would expect to see a reduction in level and gain for each of the RF muxes.  The switch datasheet indicates an average insertion loss of 0.65dB across the 0 – 2000MHz range (nominal) and maximum of 0.95dB.  Using 2x worst case (for in and out mux) we would expect to see no more than 2dB of insertion loss due to the muxes.  This would place the measured gain for channel 3 around 18.5 to 17.5dB in the sub 2GHz region.  The measurements are slightly lower than this and have more high frequency roll of than indicated by the datasheet, however, the limitations of the test equipment at this resolution of level measurement come into play above 1GHz.  In short, for this stage of characterization I am content with the initial results.

Which leaves the attenuator issue...  My first thoughts on the spurious noise were directed at an error in the QFN mounting.  I have seen multiple instances where a loose solder pad, that was not visible with a 30x loop or under the device, caused odd behavior.  Generally, these instances all involved the spurious responses changing with changes in signal level and/or frequency.  I'm left with the following options relating to the 4.7MHz harmonics: a) intrinsic to the device, b) ground pad under the device solder joint problems, or c) something in that channel's power supply/regulator.

R Board Overview

I wanted a simple way to digitally control attenuation, different amplifiers and filters, and the ability to try different analog processing quickly.  This led to another BREC board with simple RF processing (R Board).  It can also be viewed as a QFN practice board since there are several small, simple and cheap QFN parts that can be used to refine assembly techniques.

The R board (or RF input) is designed to produce better RF isolation and level control along with band specific processing.  Four channels are available using an RF mux.  Each channel has a different attenuator or amplifier present.  Channels are selectable via an SPI interface.  The board can act as a stackable A-board daughter board.

The module block diagram is:

A channel is selected via the SPI interface.  The SPI interface is implemented in two chained serial shift registers to reduce IO pin count to the BBB.  Each channel has a separate regulated 3.3V low noise supply.  When a channel is selected, the mux path is enabled and the regulator enabled.

The RF switch used is an SKY13384 (non-reflective).  It provides 4 channels that are usable from 20M-4GHz. When a channel is not selected it is terminated in 50 ohms.  A mux is used on the input and output side of a channel.  Care must be taken in user defined channels to note that when not selected a channel’s input and output has a DC path to ground through 50 ohms.

Channel 0 is a small band specific daughter board connected via two 6X1 headers.  These headers include the RF input and output, +5V (BBB supply), a digital supply enable, and two digital signals from the SPI output register (All digital signals are 3.3V logic).  This channel is designed to be small and readily pluggable.  A daughter board is roughly the width of a BBB and carriers (~2.1 inches) and can be an inch or less wide (slightly wider to cover forward mounting bolts if desired).

Channel 1 is a digital step attenuator using the SKY12347.  This is a 6 bit attenuator providing 0.5 to 31.5dB of attenuation from DC to 3GHz.  It is used in a parallel configuration.  It is only available in a 24 pin QFN package (like most attenuators at this point).

Channel 2 is a BJT amplifier - either common base or common collector configuration.  It includes 0805 L and C components configured to provide impedance matching as well as tuned or resistively terminated ports.  Final user values and components determine the configuration.  The BJT layout is targeted at a BFR93A SOT23 package (or any similar footprint).

Channel 3 is a broadband amplifier using the AD8354 providing approximately 20dB of gain from 1MHz to 2700MHz with 50 ohm termination and a noise figure of about 4dB.  It is operated in the 3V mode.

As built schematic :

As built unit #1: