Source Code Migrated to GitHub

The source code has moved to GitHub at https://github.com/drone32768/BREC

Prj137 BBB and ADC Spurs

While the overall noise floor of the updated ADC was quite good, a couple of low level spurs were present that I wanted to understand.  These show up at 2.004699MHz and 2x (~4MHz) on the particular unit under test.  After unrolling the spurs and taking measurements at a couple of different sampling frequencies they began to really look like 2 and 4MHz, not some higher frequency.  On a quick review of the data sheets for the parts on the board and BBB the first candidate was the BBB primary regulator (TPS65217C). This includes a switching regulator operating at 1.95MHz to 2.55MHz (nominally 2.25MHz).

In a quick attempt, a 10uF bypass capacitor was added across C106 on the SYS_5V supply.  This did make a few dB of improvement in the spurs so I thought I was on the right track. Another 10nF shunt capacitor was added on C119 but to no additional help.

Just to get myself calibrated, the first spur is on the order of -93dBFS which translates into 22uV RMS.  The ADP150 datasheet shows a power supply rejection ratio (PSSR) of -35dB to -40dB for 2MHz and 4MHz.  The amplifier datasheet quotes at least 55dB of PSSR.  The ADC does not quote a PSSR but one would expect at least 20dB - 60 dB.  The board has separate analog and digital power which are decoupled with a SMT choke.  Given all of this I expected to be able to see the source of noise of the board using just a simple scope probe.  On poking around on the board both digital, analog, and supply input - no luck, nothing even close.

In an attempt to do better than a simple oscilloscope probe, a white wire from SYS_5V pin was brought out to a 10uF on a spare SMT pad on the board.  This was then jumpered to an SMA connect which was then attached to a spectrum analyzer.  A picture of that setup is below.

SYS_5V spurious measurement

Low frequency scans were taken with the BBB off and with it on and the ADC operating for comparison.  Those results are below.

Low frequency spectrum with BBB powered off and with it on and ADC operating.

The really low frequency response of the SA used may not be so great (only quoted down to 1MHz), however, the spurs at 2MHz and 4MHz are clear.  The rest of the spectrum up to 100MHz was investigated as well (just to make sure that the source really wasn't a higher frequency and rolling into the low end).  The spectrum was clear (other than the 10MHz ADC sample clock harmonics) while the ADC was operating.

The 2MHz spur at -65dBm above corresponds to roughly 126uV RMS while the -93dBFS from the ADC spectrum corresponds to 22uV.  126/22 = 5.7 which translates to -15dB of attenuation. The bottom line being there is not a whole lot of PSSR compared to what one would expect.

Just to make sure I wasn't doing something silly like pushing the regulator too hard and causing problems I decided to revisit the current consumption budget on the board re-checking the dynamic component.  The following table captures that.

ADC Board Current Consumption

Even factoring in the current from digital and clock IO and using a full swing signal from the amplifier (which this measurement does not have), the current draw on the regulator is a little over half its rating.  Even if the digital line load capacitance is twice what this assumes, the current load would be two thirds the rated 150mA.

With the above in hand, I went back to the board to evaluate the spectrum at different points on the supply using the same setup as above.  The following graph compares the spectrum at the 5V source, 3.3V on-board regulator output and the 3.3V regulated output after the supply choke into the analog section.

Low frequency spectrum of supply line at various points on the ADC board.

No surprises here at the 2MHz noise.  The 4MHz is interesting in that sometimes the noise is pronounced but generally quite low and not noticable on this measurement.  (The envelope history of the analyzer is used so it depends on how long you observe it for and what you are doing - a "shutdown -h now" always creates a period of 4MHz activity).

At this point it seemed that the noise was more subtle than just supply ripple.  With that idea I revisited ground loops (where you won't directly see the currents only the artifacts afterwards and points at which you cannot access for measurement).  The ADI MT-031 application note does a good job going through the various aspects of mixed signal grounding in different environments. With this I realized I did exactly the wrong thing by isolating the analog ground plane with a choke. This would have been ok if I had directly tied the two together at the ADC (as one of the examples in the paper shows).  Fortunately, this was easily addressed by removing the choke (L101) and jumpering across the exposed ground plane edges near the ADC.  The spectrum below was taken with that configuration.

50 ohm grounded input with jumpered grounds

The spurs at 2MHz and 4MHz have dropped about 3dB relative to the choke coupled ground and are now at -100dBFS (marker 3) and -95dBFS (marker 1).

So in the end, the noise environment on the ADC ok.  Even factoring in recommended PCB layout techniques and best practices with ADCs (at least as best as I could do with the tradeoffs presented in a 2" x 3" two layer PCB) there are still switching related spurs.

Prj137 ADC Noise Floor

The first step with the updated ADC is to revisit the noise floor.  To understand just the ADC contribution the zero ohm elements at L106/L103 were removed.  This leaves the ADC inputs open with a 75pF (C115) across them with the 5ohm series inputs which roughly acts as a grounded input. The following is the 10MSPS spectrum.

ADC approximate grounded input spectrum at 10MSPS

The source of the spurs near 2MHz and 4MHz is not clear and will have to wait for another day. The real point of interest is the noise floor at -108dBFS (marker 9 in the above graph). This is in line with the vendor data sheet which shows -110dBFS by my reading of the graphs. There are a few dB of ambiguity due to the width of the noise and using different FFTs and averaging.  I am comparing mid points of the estimated noise band.  Those datasets are also using the 2V range with a transformer while this configuration is using the 1V range.  The datasheet indicates this will "degrade the SNR by 3.8dB". The details of this are not evident to me but I'll go with it.  This would then put the results on par with the datasheet.

The next step is to add the amplifier and ground its input with a 50 ohm SMA terminator. The only filtering present is the shunt 75pF capacitor at C115.  That spectrum is below.

Prj137 50 ohm grounded input.  Amplifier with ADC noise floor at 10MSPS.

Again, marker 9 is at the estimated noise floor and is showing a noise floor of -107dBFS. This is actually better than I expected.  The buffer amplifier is adding very little noise. The gain setting for this configuration is Rg=25 ohms / Rf=294 ohms or Av=11.7 which is more than many buffers of 1 or 2.

Finally, a histogram was taken of the grounded input configuration. Looking at the frequency spectrum and time series provides a lot of useful information in tracking down problems but I have also come to appreciate the value of a histogram.  The initial efforts with this board over looked a software work around from the previous board where some of the LSB were incorrectly masked.  This was not at all obvious in the grounded input time series or spectrum but was very clear in the histogram.  The following is the histogram of the 50 ohm terminated board input with amplifier (same as previous spectrum).

The VCOM bias point sits right between codes 2053 and 2054 and is only a mV or so from nominal value at 2048.  All other bins not shown were verified to be zero.

As points of reference, the LSB is 1V / 2^12 = 1/4096 = 244uV.  For noise evaluation using the processing gain of the FFT the -90 dBFS RMS voltage is dBFS = 20 * log10(Vnoise / 0.5V) or Vnoise = 0.5V * 10^( -90 dBFS / 20 ) = 16uV.