Thursday, April 2, 2015

Prj137 ADC Noise Floor

The first step with the updated ADC is to revisit the noise floor.  To understand just the ADC contribution the zero ohm elements at L106/L103 were removed.  This leaves the ADC inputs open with a 75pF (C115) across them with the 5ohm series inputs which roughly acts as a grounded input. The following is the 10MSPS spectrum.
ADC approximate grounded input spectrum at 10MSPS
The source of the spurs near 2MHz and 4MHz is not clear and will have to wait for another day. The real point of interest is the noise floor at -108dBFS (marker 9 in the above graph). This is in line with the vendor data sheet which shows -110dBFS by my reading of the graphs. There are a few dB of ambiguity due to the width of the noise and using different FFTs and averaging.  I am comparing mid points of the estimated noise band.  Those datasets are also using the 2V range with a transformer while this configuration is using the 1V range.  The datasheet indicates this will "degrade the SNR by 3.8dB". The details of this are not evident to me but I'll go with it.  This would then put the results on par with the datasheet.

The next step is to add the amplifier and ground its input with a 50 ohm SMA terminator. The only filtering present is the shunt 75pF capacitor at C115.  That spectrum is below.
Prj137 50 ohm grounded input.  Amplifier with ADC noise floor at 10MSPS.
Again, marker 9 is at the estimated noise floor and is showing a noise floor of -107dBFS. This is actually better than I expected.  The buffer amplifier is adding very little noise. The gain setting for this configuration is Rg=25 ohms / Rf=294 ohms or Av=11.7 which is more than many buffers of 1 or 2.

Finally, a histogram was taken of the grounded input configuration. Looking at the frequency spectrum and time series provides a lot of useful information in tracking down problems but I have also come to appreciate the value of a histogram.  The initial efforts with this board over looked a software work around from the previous board where some of the LSB were incorrectly masked.  This was not at all obvious in the grounded input time series or spectrum but was very clear in the histogram.  The following is the histogram of the 50 ohm terminated board input with amplifier (same as previous spectrum).
The VCOM bias point sits right between codes 2053 and 2054 and is only a mV or so from nominal value at 2048.  All other bins not shown were verified to be zero.

As points of reference, the LSB is 1V / 2^12 = 1/4096 = 244uV.  For noise evaluation using the processing gain of the FFT the -90 dBFS RMS voltage is dBFS = 20 * log10(Vnoise / 0.5V) or Vnoise = 0.5V * 10^( -90 dBFS / 20 ) = 16uV.

2 comments:

  1. Not so bad!
    So the main difference with ur previous board prj134 or the main contribution to the noise was ur flying whites wires especially on the clock signal i guess and the new ferrite bead on the +3.3V ?
    I 've Looked at ur gerber files and at first i was thinking that u were wrong with ur clock signal because it is far away from it's return gndpath. But later i've discovered that ur ground plane separation is not true because u 've tied together the gnd exposed LTC2225'pad (pin33) with ur Dgnd plane.
    This is like a shunt on the L101 ferrite. In addition this make a second return path for current and it is not a good idea usually. Don't you think ?

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    1. Tom, yes the primary difference between the earlier version and this board was correcting some reset logic, correcting the clock signal to the PRU input, and adding the chokes. The clock is a challenge since it has to go to the upper right of the board (as oriented in picture) and to the bottom of the board to get to the PRU pin. In fact it has to make a hook around the part to get to the ADC input (its on the bottom to avoid the digital outputs and hooks to get around the paddle on the bottom. I wanted to keep the clock away from the FDA and input so it went on the upper left. Trying to get all of the digital lines to the PRU in the upper right, route the clock to opposite sides of the board and get the grounding right is difficult in a two layer board with the outside connectors from the BBB. After more review (the ADI app note referenced in the post), the grounding approach is flawed in that both planes should have been tied together *completely* at the ADC.
      The way it was, I think you are correct, the pin 33 (paddle) being on the digital ground may act as a shunt when L101 was present and this would present a loop. This wasn’t the intent, just thought my options at the time were to pick one or the other side.
      The last ADC spectra is taken with the L101 (gnd coupling) choke removed completely, and a strip soldered between the two grounds (up by C118 in the picture bridging the unmasked edge of panes – I did not post picture it since this and the choke removal were the only difference). I’m not really convinced this is the full story yet. I could do a better job tying the grounds together near the ADC and will probably try that, however, I expected more improvement with just the choke removal, tie by C118, and paddle so suspect there is more to this than I am currently seeing. I want to get through gain verification and harmonic distortion measurements before revisiting the grounded input (If is the worst spectrum artifact at -95dBFS I will be happy).

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