RF Level Control Board (Prj135)

While waiting for the fab of an updated high(er) speed ADC board I returned to another project in progress. The goal of that effort is to develop a board that provides some amount of level control as well as coarse power measurement.  Out of this came the L board or Prj135.  The idea is to include two stages of amplification with a digital step attenuator in between.  At the final output a power meter samples the output. Control of the board is a SPI like interface using the I board from previous work. The block diagram is shown below.

The component selection was straight forward.  I wanted to stay within a 3.3V supply and had used the AD8353/8354 successfully in the past across a wide bandwidth.  For the digital step attenuator I wanted to try a CMOS based part such as the PE4302 to see if I could avoid some of the problems encountered in the past. For the output power assessment I did not need a large dynamic range so decided to go with an RMS power meter.  The LTC5587 is nice as it includes an integrated ADC.  Since I wanted to be able to use the board at low frequencies I went with a power divider/resistive coupling between the output and the detector. The schematic for the board is shown below.

Level Control Board Schematic.  Control and power via 10 pin header from a Beagle Bone Black interface board.

The last time I worked with a digital step attenuator there were two issues encountered.  First, there was low frequency impulse noise (and here).  Second, at a board level the higher levels of attenuation were not achieved (assumed to be the switches and overall layout and proximity of input and output ports).  The current approach allows plenty of isolation between the RF ports and shielding.  I decided to proceed slowly and first evaluate the attenuator.  Shown below is a picture of a partially assembled board.  Only the attenuator in the center is populated, with the amplifers at left and right unpopulated and jumpered over.

RF Level Control Board. AD8353 amplifiers at left and right.  PE4302 digital attenuator in the middle.  LTC5587 power meter in lower right.  Control and power lower center. The form factor and bolt holes match the BBB.

A couple of quick tests showed most of the attenuation range achievable and a fraction of a dB in insertion loss at sub 1GHz frequencies.  Higher frequencies showed some degradation in both, however, with the jumpers and no shielding I expected this.  The best part was no impulse or other unexpected noise to at least -90dBm (my measurement limit). The next step is to evaluate the RMS power meter and output coupling to it.

ADC Measurements

Before taking any meaningful measurements with the 10MSPS ADC board I took the time to update the software.

Software Updates

The BBB PRU software was updated to normalize the data samples to 16 bit unsigned.  Unfortunately, the 2 most significant bits from the ADC are not accessible on this board (During design, I went back and forth with the 14 bit version and in one of the rounds of updates shifted the data lines wrong). This has two implications.  First I cannot use levels higher than quarter scale or -12dBFS. Second it also means there is some bit manipulation required to make the quarter scale values come out correctly.  I also took the time to factor out multiple PRU images to support programmable down sampling or filtering images.  To support this I optimized the benchmark software a little to recoup a few instructions.  The basic difference is that spinning waiting for clock transitions is done using a quick branch bit test and the communication of the sample fifo pointer between PRUs is done using a XIN/XOUT side transfer instruction rather than SRAM accesses. (source code is under the H board directory or here ).

The PC analysis software was updated to better handle the higher sample rates. The tools I used were developed over time with sample rates that were less than those supported by 100Mb Ethernet and PC processing. The original version allowed use of UDP and directly following the input stream.  At 10MSPS the Ethernet and PC do not keep up so a switch to using TCP with collecting coherent snap shots was implemented. Both approaches have their merits depending on what you are trying to do with the data and testing. (source code is the "ADC" sub application under the Other directory here )

The following results are from the PC ADC utility that takes a snapshot of coherent data samples, does an FFT with windowing, and averages the results.  All results are in db full scale (dBFS).  All of the results include a history envelope in green which captures the maximum and minimum excursions measured.

Noise Floor

Once the software was updated, the first step was to check for board level noise sources.  The following is a spectra capture with the input tied to ground via a 50 ohm resistor.

ADC at 10MSPS with 50 ohm resistor to ground at input.

While the ADC has differential inputs and better common mode noise immunity I was a little concerned about using the op amp as a single ended to differential conversion with gain (specifically, picking up noise from the BBB).  Fortunately,  there are no surprises here.  Things are nice low and flat across the band.  The average noise floor is a little higher than the vendor datasheet (about 14dB for the same size FFT), however, I expected this somewhat since I have a +20dB amplifier before the ADC and the reference results use a transformer input.

SFDR

The next step was to measure spurious free dynamic range. The largest challenge in this kind of measurement is getting the source harmonics at the input lower than the harmonic levels you are looking to measure at the ADC.  To do this I used a DDS with a 2x cascaded 10.7MHz ceramic filter with a 3dB pad between them to avoid coupling.

This ends up being more complicated than originally expected for a couple of reasons.  First the filter responses at harmonics are not provided by the manufacturer.  The response curve only goes out a few MHz from the filter center.  My understanding is that depending on construction techniques some ceramic filters are susceptible to reduced harmonic rejection due to the mechanical properties of the filter.  If you just assume the harmonic rejection is as good as the stated close in stop band you would expect 70dB of rejection in a 2x cascade.  The DDS produces harmonics that are 20-30dBc.  Taken together we hope to get -90dBc harmonics at the ADC input.

Better than hoping would be to measure.   Unfortunately this is where the harmonic spurious response of the spectrum analyzer comes in.  While measuring the harmonic levels, the fundamental is kept within the passband of the filter and at a high level to bring the harmonics up to a detectable level.  This produces a harmonic response within the test equipment which you cannot differentiate from the harmonics from the device under test.  In conducting this kind of measurement I get harmonics of -60dBc or lower.  A better approach would be to use high pass or notch filters after the device under test to reduce the overall levels into the spectrum analyzer.  The point of this all being that the source harmonic content is someplace between -60 and -90 dBc.

The LTC6406 datasheet shows a second order SFDR of  at least -90dBc.  The LTC2225 datasheet indicates a SFDR of -76 to -90dBc.  The source is the weak spot with a 2nd harmonic of -60 to -90 dBc.

Once the input signal and harmonics were understood better, the next step was the DDS spurs.  I selected frequencies of 10.640MHz and 10.800MHz for evaluation as the spurs at these frequencies were far enough from the fundamental to be caught in the stop band of the filters.  In between these frequencies the spurs varied from 100kHz to 200kHz from the fundamental and landed within the passband of the filter.

The following is a capture of a 10.640MHz filtered input.

10MSPS LTC2225 with LTC6406 Av=10 amplifier capture at 10.640MHz.  Note: only marker #4 is a harmonic, the others are DDS spurs.

At 10MSPS the 10.640MHz signal and harmonics show up at 0.640MHz, 1.28MHz, 1.92MHz, and 2.56MHz.  The only harmonic visible is the second at marker #4 at -87dBFS (This does a fair amount of bouncing and is often not visible, the capture was taken at a peak).  The third harmonic which has an even higher level at the board input is not even observable.  The other signals in the plot are DDS spurs. The fundamental is at marker #1 at -13dBFS.   Based on this we get a 87-13= -74dB SFDR.  

As a sanity check, 10.800MHz was checked.  That spectra is shown below.  

10MSPS LTC2225 with LTC6406 Av=10 amplifier capture at 10.800MHz.  Note only marker#6, 7, and 5 are DDS spurs.

Here the signal and harmonics are at 0.800, 1.6, 2.4, 3.2, 4.0, and 4.8MHz. Unlike 10.640MHz, only markers 5,6, and 7 are clearly DDS spurs whereas the rest correspond to 10.800MHz harmonics.  Just focusing on marker#2 at -87dBFS and the fundamental at -16dBFS we get a differences of 71dB.  This is close to the the results at 10.640MHz and considered within my measurement uncertainty relative to part specifications.  It is interesting to note that the third harmonic is not visible while fourth, fifth and sixth are visible and only slightly less that the second.

Just for grins, I decided to scan the filter envelope with the ADC.  The ADC has much better resolution in frequency and level than any of my test equipment so once you can believe the results its a useful setup.  The following is a 10kHz step scan across the filter using an FFT size that yeilds a bin size roughly equal to the step size.  The markers were manually chosen to follow the envelope.

Filter scan using the ADC.

With this setup I'm within the region of evaluating source/filter harmonics versus internally generated within the amplifier or ADC.  The next logical step would be to correct the PCB to allow using true full scale and use a better source and filter set. So without spending alot of time and energy on better sources and filters I'm going to stop here and call it 70dB or better of SFDR.

10MSPS ADC with a BeagleBoneBlack

I wanted to revisit the ADC board used previously with a BBB for SDR and instrumentation work. The first version used a serial ADC with a PRU.  It produced acceptable SDR results (and here and here )  However, for instrumentation work the SFDR was less than desired due to amplifier selection (saga described here).

The first goal was to increase the sample rate without resorting to an FPGA.  Previous measurements and benchmarks indicated that 10MSPS should be possible.  Additional bits of resolution was also a goal.  Most serial ADCs at 14+ bits do not have sample and hold bandwidths high enough for use in the intended subsampling application.  In addition, getting to just 2.5MSPS using a serial interface is challenging using only a PRU to clock the data. I decided to start simple and use a parallel part with a differential input.  The LTC2225 was selected as it supports the desired sampling rate, has a large SH bandwidth, is reasonably priced, readily available, and has a 12 and 14 bit variants.

Another goal was to stack the new ADC board with an existing IO board thus allowing a single BBB to control mixers, gain and filter boards.  The led to PRU1 being used to interface with the parallel ADC.

The following is a block diagram:

BeaglBoneBlack 10MSPS ADC board

There were some errors and difficulty involving the power on reset circuitry (PRU1 R31 uses pins that are shared with the system boot mode selection).   The following is a picture of the updated and functional assembly (white wires and all).  Given the changes I will post a schematic once the PCB has been updated.

10MSPS ADC mounted on BBB.
TCXO upper left, LTC2225 upper right, LTC6406 bottom right, regulator and power-on circuitry lower left.

Even though it can't be stacked yet, its good enough to take some measurements and work on the software for higher sample rate processing.

Interface Board Updates

An interface board was developed to provide 3 ports of 6 discretes and +5V in a 2x5 header connector.  It also allows high side switching of the +5V supply. The first version is described here. I did not properly check the power-on state of the enable gpios. I also realized that I should have buffered all of the pins.  Most digital IOs have ESD protection diodes.  What this means is if you are not careful, a digital high voltage can partially power the part when the main supply is switched off.  This has the negative effect of raising a pin above VDD (which is ~0) and can damage the part.  The software worked around this by ensuring that when the supply was disabled all IO pins were at 0.  I took the opportunity to correct this and add a FET buffer between the BBB gpios and the connector pins.

There was one error on the board where the inputs to an inverter were swapped (NC was connected to the input).  By using a NOR gate in the same package rather than the inverter I was able to correct this without a white wire.  The schematic is shown below.

There is one pin unused (PRU1_R31_15) on the P9 connector to allow stacking with a board using the rest of the PRU1 pins on P8.

Prj133 Mixer at 1575MHz IF (Part 2)

Given the issues with the high frequency balun, I populated the synthesizer and discrete balun for a 1575MHz IF output.  The schematic can be found in this post. The balun values used are shown below.

Component	Value	Comments
C105/C113	120nF	DC blocking capacitors
L102/L103	6.8nH	DC supply chokes
L107/L108	10nH	4:1 Lattice Balun inductor
C106/C107	1pF	4:1 Lattice Balun capacitor

The following is a picture of the final assembly:

Synthesizer (ADF4351 - left off center) and Mixer (LTC5510 - right center) using a 1575 MHz discrete balun (upper right).  Power and digital interface at left via 2x5 header.  

This was then used to sweep 200MHz about an IF of 1575MHz using various RF input frequencies.

The measurement device has an uncertainty of +/-2 dB.  The input RF level should remain fixed, however, its level can be pulled a dB or so with load reactance.  So the +/- dB wobble across the IF band is not a surprise.  The level falling off with increased frequency is also not a surprise given the board loss with the LO at 3.2GHz for the higher RF input cases. 

Prj133 Mixer at 1575MHz IF

The most significant challenge has been hand mounting the high frequency output balun.  The part is so small and only has 6 small pads that it has proven very difficult to seat properly.  Even the smallest amount of excess solder causes the part to not self align properly leaving one of the pads open.  Unlike some of the QFN parts I have used there are not enough pads to create enough surface tension to decently self align.  In the process of wicking off excess solder it is very easy to wick off too much and again wind up with an open.

In an attempt to address these difficulties, I started by mounting the balun first without any other components and measuring the resistance between the pads at the board level to ensure there were no opens.  The following is a picture of that.

This produced an output that was about 10dB lower than expected.  In retrospect, I may have been having problems using the external LO port and getting enough power into the mixer coupled.  In addition there uncertainties in drive level (+/- 5dB) and measurement level (+/- 2dB).  In short, I had myself convinced an open had appeared and proceeded to rework the part mounting.  This led to more problems with opens and alignment. Finally, I ended up tearing off a couple of pads by accident.  The part is so small with only 6 pads its easy to accidentally move it as the solder is not fully at temperature.  The figure below captures that saga.

The top part has missing pads and the bottom part is for reference.  Pin one indicator at left.  Pin 6 pad is missing while pin 1 is partially lifted. The trace to left of parts is 0.2mm, the C146 lands are for an 0805 part, the ground plane vias are 0.89mm diameter.  At this point, the discrete balun was looking pretty good ...

The overall mistake was to use orthogonal pads.  The datasheet for the balun recommends taking the corner pads out at a 45 degree angle.  This would have given enough vertical and horizontal pull to self align including the middle two pads.

Prj133 Mixer at 315MHz IF

Admittedly, using a 10.7MHz IF is not very challenging, however, it was a good first step to understand the PCB, the LTC5510, and the balun responses.  The next step was to use a higher IF.  315MHz was chosen due to the wide spread availability of low cost SAW filters.  The following captures that construction.

Initial measurements showed what appeared to be some shunt capacitance between the differential output lines.  Based on frequency response roll offs it looked like about 2pF.  This is higher than I had hoped.  I cut the traces to the pads for the high frequency SMT balun hoping this would alleviate some of that (it did not).  The DC feed chokes for the differential outputs were reduced from 1uF to 39nF in an effort to use them to cancel the shunt capacitance.  The table of final values used is shown below.

4:1 315 MHz Balun Part	Value	Comments
C105/C113	1nF	DC blocking capacitors
L102/L103	39nH	DC supply chokes
L107/L108	47nH	4:1 Lattice Balun inductor
C106/C107	5pF	4:1 Lattice Balun capacitor

 
Measurements were taken with a 1220MHz RF input at -15dBm while the LO was high side swept.  Those results are shown on the following graphs.

Based on the above figure the mixer gain is on the order of a dB or so at the frequency response peak.  This is within expected results all things considered (the uncertainty of the test equipment is +/-2dB).  The LO bleed through is roughly -40 dB while the RF bleed through is -25dB.  The data sheet at this supply voltage and with these frequency ranges indicates both should be <= -40dB.  The LO is fine while I suspect the RF to output port isolation is lower than the device due to PCB level issues (layout/proximity/groundplane on a routed 2 layer board).

I have noticed that a higher frequencies it is difficult to get enough power into the LO port.  The dog leg input is not helping me here but was only for early testing and sampling.  I suspect the "stray capacitance" I thought I was tuning out was a function of measurement uncertainties and LO power input roll off.  The final version will populate the on board synthesizer which has a nice impedance controlled direct differential input with the necessary power output. At this point the behavior is good enough and within expectations to move on to using the high frequency output balun.