Saturday, September 6, 2014

Interface Board for Beagle Bone Black

The stacking of the boards has worked out well.  It provides a nice compact foot print.  By using a couple of 2x5 headers only the first board in the stack needs the full connector set.  The first board also generally needs additional pins and higher speed IO.  This allows boards higher in the stack to recoup some board space and use fewer pins for less insertion/extraction force.

The only short comings of this approach have been: a) current/power supply limits, b) lack of properly sequenced 5V supply, and c) difficulty in shielding and isolating the boards.  To address these I created an interface board (I-board, to go with the A/B/C/R BREC boards) that drags out some gpio's and provides system 5VDC rather than the regulated 3.3V supply.

Part of the goal of this project was to preserve all of the PRU pins for higher speed digital interfaces (to DACs and ADCs).  This would allow an I board to stack on top of an ADC or DAC board and then provide several other shielded boards with a power and gpio based SPI interface.  A couple of pins were reserved for discrete in/out status.  The model was the synthesizer and RF front end boards (B/C/R).  Below is a picture of the first version of that board.

Beagle Bone Black Interface Board
The ability to power down a board to quiesce any signals it may be generating is a very useful aspect in RF configurations so it was important to have a supply switching capability. Each port contains two ground pins and two system 5VDC lines.  The supply lines derive from the BBB VDD system 5V directly from the external supply.  They are routed through high side supply switches.  I used the MIC94073.  This part includes a digital enable (that works with 3.3V logic), capacitive discharge and soft start.  This provides enough current for most of the boards of interest while staying within the current carrying capabilities of IDC.  It also provides a supply sufficient that most 5V regulators can be used to produce a regulated version within specification on the daughter board.

There are PTC fuses on each port.  To try and make things less exciting for day to day work, power and ground lines are at opposite diagonal corners of the header pin mapping.  This way if you accidentally rotate a connector by 180 degrees you are not guaranteed to short supply to ground (your mileage may vary on the rest of your pins based on assignment).  The other 6 pins of each port are connected to BBB gpio lines.  These can be any configuration desired and switched at run time.  The source code on google code contains the default mapping and direction(under Iboard).  The software configures all gpio pins back to input when a port is powered down.

To test the software and evaluate hardware startup a small test harness was created with LEDs for visual inspection of lines and through hole components with loops you can get a scope probe on or a jumper clip to route digital outputs back to digital inputs.  The following is a picture of that harness.
10 Pin Port Test Harness
It was fun going back to assembling something using through hole components and things you don't need a magnifying glass and tweezers to work with.

The power on sequencing of ports and supply power is the only interesting aspect of this kind of activity.  Now you might think - "gee, how hard can it be to screw up something like that".   I have been using the Beagle Bone Black System Reference Manual (SRM) A5.6.  There are a couple of passing references to SYS_RESETn and gating signals with it, specifically the boot lines.  By version C.1 of the SRM there 5 instances of large, bold, red text indicating "NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH."  So apparently, I am not alone in failing to pay proper attention to power on sequencing (not that I should have needed to have this in the SRM, this is one of those basic digital design things I can still see my old professor just smiling, shaking his head, and calmly waking away...).  This revision of the board does not use the appropriate gating but is easy to correct, consequently I won't post the schematic until I update and retest.

The other interesting aspect of this is the initialization state of the pins following SYS_RESET.  If you look at the Sitera Processor/am335x "data sheet", TI SPRS717G you see Table 4-1 called "Ball Characteristics".  This table provides the state of all pins, specifically the gpio pins of interest, and the state they are in by default after reset.  They will sit in this state until your cape overlay gets loaded (which can be several seconds).  You can modify uboot to update them, however, there are still hundreds of milliseconds until this can occur.  The point being that I used 3 gpio's to drive the high side supply switches for external power to each of the ports.  I did not choose carefully enough and consult the SPRS717G with respect to initial state. I wound up using lines which, while inputs, default to having pull ups.  This is enough to enable the port supply lines immediately following reset.  The original goal in allocation of gpios was to preserve most of the P8 connector lines for PRU input/output while using as many gpios from P9 as possible.

The bottom line is; given the IO and boards I am working with in the near future this version is good enough and will not drive IO pins prior to it being safe to do so, however, the power on sequencing needs to be corrected for general use.This is also a good example of why if you are going to use the BBB unregulated supply additional care and consideration should be taken.


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