Interface Board Updates

An interface board was developed to provide 3 ports of 6 discretes and +5V in a 2x5 header connector.  It also allows high side switching of the +5V supply. The first version is described here. I did not properly check the power-on state of the enable gpios. I also realized that I should have buffered all of the pins.  Most digital IOs have ESD protection diodes.  What this means is if you are not careful, a digital high voltage can partially power the part when the main supply is switched off.  This has the negative effect of raising a pin above VDD (which is ~0) and can damage the part.  The software worked around this by ensuring that when the supply was disabled all IO pins were at 0.  I took the opportunity to correct this and add a FET buffer between the BBB gpios and the connector pins.

There was one error on the board where the inputs to an inverter were swapped (NC was connected to the input).  By using a NOR gate in the same package rather than the inverter I was able to correct this without a white wire.  The schematic is shown below.

There is one pin unused (PRU1_R31_15) on the P9 connector to allow stacking with a board using the rest of the PRU1 pins on P8.