Prj 141 - Spartan6 LX9, ADC, and BBB (Part1)

With some work on the VHDL another unit was constructed with an ADC.  One of the advantages of using an FPGA assembly like the XuLA2 is that it can be moved from one carrier application board to another.  The schematic is shown in the previous post.  A picture of the final assembly is shown below.

Prj 141 Unit #2.  BeagleBoneBlack with SPI interface board at left.  Right hand side is ADC carrier (purple) with XuLA2 including a Spartan6 LX9 (green).

The one white wire shown is a regulator enable that I decided at the last minute to statically pull up rather than drive from the FPGA.

The VHDL was developed incrementally from the base digital/SPI interface into a single channel digital down converter.  All of the VHDL is available here.  The summary block diagram is shown below.

Block Diagram of Digital Down Converter for Spartan LX9 with SPI Interface

The inputs to the FPGA (Spartan6 LX9) are a 12 bit ADC input with sample clock, a 12MHZ digital clock input and a SPI interface.  The outputs are 4 LEDs for testing and a SPI output.  The sample clock is designed to be 10MHz to 100MHz.  All IO pins and timing constraints are specified in the UCF file.  The top level break down includes a digital block for interfacing to the processor, a signal block for interfacing with the ADC and processing the signal.  A 4k x16 bit FIFO buffers the data from the signal processing to the control block and processor.  The control block gets a digital clock which is multiplied up by 4 using a DCM to interface with the processor SPI.  It also receives a copy of the ADC sample clock for testing and diagnostic purposes.  The control block receives a status set of discretes from the signal block and provides to the signal block a set of control discretes.  The TPG discretes control the internal generation of test patterns, the FSS (Fifo Source Select) determines which internal signals are placed in the sample FIFO between the signal processing and digital interface and the PINC (Phase increment) determines the frequency setting of the signal block DDS or NCO that gets mixed with the ADC input.

There are two major clock domains within the part: the sample clock and the digital clock.  The signal processing block is driven entirely by the sample clock while the control block is driven completely by the digital clock (from the DCM).  All information between the blocks is through a FIFO with separate clocks or via discretes that are re-clock synchronized at the destination.

A couple follow on posts walk through some of the details.

Related:
Prj141 Schematic
Prj141 Overview
Prj141 Digital Down Converter
Prj141 Digital Interface
Prj141 Software
Prj141 Filter Design
Prj141 Filter Evaluation
Prj141 LX9 Utilization
Prj141 Higher Sampling Rates