Sunday, November 15, 2015

Prj141 - Digital Down Converter Signal Block (Part2)

The signal block of the FPGA (overview here) is a simple digital down converter.  You could just use a Xilinx core, however, since this was my first project with VHDL I wanted to assemble the pieces myself (and I wasn't sure I could correctly use the generated core as are geared to multi-channel and much more complicated applications, besides that, it is more interesting and instructive to walk through a full DDC on your own at least once).  A block diagram of the signal block is shown below.
Single Channel Digital Down Converter Block Diagram
The VHDL source is here.  The signal processing block is a single channel digital down converter using separate Xilinx cores.  The 12 bit ADC signal comes in at the left and is formatted (unsigned to signed conversion). There is a mux which selects the ADC stream or an internally generated test pattern to be sent to separate I and Q multipliers (S_s12 in the block diagram).  The multipliers are driven by the sin and cos outputs of a Xilinx DDS generated core.  The DDS frequency is controlled by its phase increment register.  This register is written by a FSM in the AXI register block.  It takes a 16 bit wide set of discretes, buffers them and when they change writes the new value to the DDS core.

The output of the multipliers is fed into a CIC filter generated core.  The CIC is on the order of N=4 while the decimation is on the order of 50 to 300.  (the exact parameters depend on both the sample clock rate populated on the board and the detailed design of the filters downstream).

The CIC outputs are sent to a compensation FIR filter generated core.  The FIR filter is designed to compensate for the droop in the pass band of the CIC filter as well as to provide antialiasing for a decimate by 2 at this stage.  There are several good applications notes from both Xilinx and Altera on balancing the tradeoffs with CIC filters and FIR filters and decimation.

The low rate signal data from the I and Q chains is taken from the CFIRS by the IQ writer block and written to the FIFO a pair of samples at a time.  This block is implemented as a FSM which waits until both I and Q samples are ready and then writes both values to the FIFO.  Care needs to be taken at this step since the FIFO data can easily be shifted by 1 during starts/stops/resets.  If this happens the consumer of the data ends up reading I(n),Q(n+1) as a complex sample which represents a phase shift and results in not truly quadrature signals.  For this reason the FSM includes special logic to write a pair of samples or none at all.

Lastly, there is a mux which selects which data is presented to the FIFO write signals.  Based on the FSS (Fifo Source Select) discretes, samples from any point in the processing string can be sent to the FIFO. The FS designator on the block diagram shows the setting to select data from that point in the chain.  This capability might sound like a nicety, but is absolutely essential to developing, debugging, and integrating the software and firmware.

Similarly, the test pattern generator is immensely useful for a couple of reasons.  First it allows the use of clean known digital signals.  These can be specified at a precise frequency and amplitude.  Second, it serves as a reference for down stream software development without having to have a physical signal generator attached to the system.

There are a couple of other important aspects not shown on the block diagram for brevity and clarity. The entire signal processing block is driven by the ADC sample clock and is designed to work from 10MHz to 66MHz.  There is an internal reset used to reset the filters (i.e. ensure they all start on the same sample and have no residual samples from previous operations).  This is driven by the FIFO reset from the control section.

Prj141 Schematic
Prj141 Overview
Prj141 Digital Down Converter
Prj141 Digital Interface
Prj141 Software
Prj141 Filter Design
Prj141 Filter Evaluation
Prj141 LX9 Utilization
Prj141 Higher Sampling Rates

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