Wednesday, January 20, 2016

Prj 141 - DDC Filter Evaluation (Part 6)

The previous post walked through the design of the DDC filter and this note covers the evaluation and measurement of that filter. The following are links for Part1, Part2Part3Part4 and Part5.

The DDC filter was evaluated by updating Xutil (here) to scan the filter response.  This is accomplished by using the built in test pattern generator used to generated DDC input data having a 1.25MHz square wave [ 1/8th Fs ]. The DDS internal frequency was swept from this to +500kHz.  At each step 2k samples are collected, have an FFT done on them and the peak is picked across the spectrum.  These values are normalized to the first response (at DC) and converted to dB.  The following figure shows those results compared to Octave calculations. 

Firmware 0603 DDC Filter Response Measured vs. Predicated.  See text for measurement technique used.
The measured values agree quite well with the predicted response.  The passband noise floor being somewhat high is suspected to be due to the fact that peaks were picked in the response and the input is not a true tonal input rather a square wave. This would result in harmonics being present across multiple Nyquist regions which may end up being selected as a peak in the cases where the fundamental response is quite low.  In addition there is quantization between the CIC and CFIR stage as well as at the CFIR output stage (all to signed 16 bits) and the input is only 12 bits.  Due to all of these I am not concerned about the stop band region.  The peak responses in the 2nd and 3rd Nyquist regions align well with predicted and indict there are no missing factors of 2 or pi lying around anywhere in the modelling or implementation. 

The same setup was used to evaluate ripple in the passband and is shown below.

Firmware 0603 DDC Filter Passband Ripple Evaluation Using FPGA Internal Test Pattern Generator.
Fc/R = 0.25 is the CFIR cutoff frequency.  The design backed this up to Fc/R=0.225 to provide some margin.  This is the source of the tail of the response prior to 50kHz.  

The final part of the evaluation is to use a real analog input rather than the internal test pattern generator.  Those results are shown below.

Firmware 0603 DDC Measured Response with Signal Swept Through Passband
The figure was generated by using an external analog input (DDS filtered through a 2x 10.7MHz ceramic filter).  This was stepped in 100Hz increments on the left and about 1kHz on the right.  The envelope history was enabled and produces the green line.  The subtle level variance is due to the analog input variance.  This agrees quite well with the predicted and test pattern generator measured response including the small side lobe in the 49kHz region.

Prj141 Schematic
Prj141 Overview
Prj141 Digital Down Converter
Prj141 Digital Interface
Prj141 Software
Prj141 Filter Design
Prj141 Filter Evaluation
Prj141 LX9 Utilization
Prj141 Higher Sampling Rates

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