The Altera Application Note 455 “Understanding CIC
Compensation Filters” provides a good overview of both CIC filters and the
issues associated with designing compensation FIR filters for them. It includes basic Matlab (or Octave) code to
design the compensation filter coefficients.
This was used and expanded upon to plot different views of the data to
help familiarize myself with the issues and get a feeling for the trade-offs. The script used to produce all of the figures is available here.

With multi-rate filters you have to be careful and understand at what frequency
the operation is being applied at and how it translates to the up-stream and
down-stream stages. The analysis is all based on the 0603 firmware version
parameters. Those are:

- Fs = ADC sampling rate = 10MHz
- N = number of CIC stages = 4
- M = CIC differential delay = 1
- R = CIC rate change = 50,
- Final bandwidth = 100 kSPS (limited by SPI interface)
- FIR filter sample rate = 200kSPS (or 2x the final for a FIR filter decimation rate of 2),
- L = number of FIR filter taps or order = 96,

Said differently, Fs/R = 10MHz/50 = 0.2MHz = 200kHz. The CFIR decimates by 2 to yield a final
sample rate of 100kHz. The cut off
frequency of the CFIR is chosen to be slightly less than half of [ (Fs/R) = CIC
rate] / [ 2=CFIR Decimation ] or 45kHz to allow for a transition band which
yields a Fc = 45kHz/200kHz = 0.225 when normalized.

The number of CIC stages had to be limited due to the number
of DSPs available in the Spartan6 LX9. CIC
filters without DSPs higher than order 4 cause problems with the map phase of
the FPGA tools (i.e. they weren’t completing within an hour indicating layout
issues). The number of FIR filter taps
was limited to 96 to avoid requiring additional DSPs to implement this
filter. Recall, that since the DDC is
implemented discretely within the FPGA, there are two chains of CIC/CFIR one
for I and one for Q.

To get a feeling for the response across the entire ban d,
the CIC is plotted in three reference frames shown below.

CIC Filter Response |

Note that the current implementation uses a 10MSP ADC,
however, the target is 60MSPS. The
difference is whether R is 50 or 300 and does not impact the rest of the
design. There is an antialiasing
hardware filter prior to the ADC which limits input signals above Fs/2. Using the Matlab or Octave fir2() function, a
FIR filter with a response to normalize the CIC response close to unity gain
over the first CIC Nyquist interval is designed. The response of that filter looks like the following.

Compensation FIR (CFIR) Desired Response |

In this example Fs/R = 200kHz, and half of that (or the
first Nyquist region of that filter) is 0.5*Fs/R. Since this will be decimated by 2, the true
cut off frequency is 0.5 of this (slightly less in this case for some
margin). The following compares the CIC
response over the target range along with the CFIR and the total response of
the cascaded filters.

CIC, CFIR and Composite Response |

The above graphs only show the response over the CIC first
Nyquist which is the final goal for evaluating passband, however, we need to
consider the full response over multiple intervals due to the periodicity of
both filters.

CIC, CFIR and Composite Response Over Multiple Nyquist Intervals of Final Sample Rate |

Normalized Composite and Constituent Filter Responses |

Based on this figure the response is very clean up to around
0.78 Fs/R where the composite picks up to around -43dB based on the CFIR
wrapping and the CIC not having rolled off very far. The following provide two detailed views of
the passband focusing on transition region and passband ripple.

Passband to Stopband Transition |

Passband Ripple Evaluation |

In short this filter works well for the intended purposes
and fits within the LX9.

Prj141 Schematic

Prj141 Overview

Prj141 Digital Down Converter

Prj141 Digital Interface

Prj141 Software

Prj141 Filter Design

Prj141 Filter Evaluation

Prj141 LX9 Utilization

Prj141 Higher Sampling Rates

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