Prj 141 - DDC LX9 Utilization (Part 7)

As this was my first FPGA I had no feeling for what would and would not fit within an LX9. The design (see Part1, Part2, Part3, Part4, Part5 and Part6 ) takes roughly 40% of the slices in an LX9 with 17% of the slice registers and 28% of the slice LUTs being used. A single DCM is used for internal logic resulting in a 25% utilization and only 4 of 16 DSP48’s are used for a 25% DSP utilization. A full report from ISE 14.7 is attached below.

Device Utilization Summary					[-]
Slice Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Registers	2,037	11,440	17%
Number used as Flip Flops	2,037
Number used as Latches	0
Number used as Latch-thrus	0
Number used as AND/OR logics	0
Number of Slice LUTs	1,640	5,720	28%
Number used as logic	1,355	5,720	23%
Number using O6 output only	719
Number using O5 output only	98
Number using O5 and O6	538
Number used as ROM	0
Number used as Memory	126	1,440	8%
Number used as Dual Port RAM	0
Number used as Single Port RAM	0
Number used as Shift Register	126
Number using O6 output only	8
Number using O5 output only	0
Number using O5 and O6	118
Number used exclusively as route-thrus	159
Number with same-slice register load	151
Number with same-slice carry load	8
Number with other load	0
Number of occupied Slices	577	1,430	40%
Number of MUXCYs used	704	2,860	24%
Number of LUT Flip Flop pairs used	1,931
Number with an unused Flip Flop	288	1,931	14%
Number with an unused LUT	291	1,931	15%
Number of fully used LUT-FF pairs	1,352	1,931	70%
Number of unique control sets	66
Number of slice register sites lost         to control set restrictions	175	11,440	1%
Number of bonded IOBs	25	186	13%
Number of LOCed IOBs	25	25	100%
Number of RAMB16BWERs	5	32	15%
Number of RAMB8BWERs	2	64	3%
Number of BUFIO2/BUFIO2_2CLKs	0	32	0%
Number of BUFIO2FB/BUFIO2FB_2CLKs	0	32	0%
Number of BUFG/BUFGMUXs	3	16	18%
Number used as BUFGs	3
Number used as BUFGMUX	0
Number of DCM/DCM_CLKGENs	1	4	25%
Number used as DCMs	0
Number used as DCM_CLKGENs	1
Number of ILOGIC2/ISERDES2s	0	200	0%
Number of IODELAY2/IODRP2/IODRP2_MCBs	0	200	0%
Number of OLOGIC2/OSERDES2s	0	200	0%
Number of BSCANs	0	4	0%
Number of BUFHs	0	128	0%
Number of BUFPLLs	0	8	0%
Number of BUFPLL_MCBs	0	4	0%
Number of DSP48A1s	4	16	25%
Number of ICAPs	0	1	0%
Number of MCBs	0	2	0%
Number of PCILOGICSEs	0	2	0%
Number of PLL_ADVs	0	2	0%
Number of PMVs	0	1	0%
Number of STARTUPs	0	1	0%
Number of SUSPEND_SYNCs	0	1	0%
Average Fanout of Non-Clock Nets	3.37

Related:
Prj141 Schematic
Prj141 Overview
Prj141 Digital Down Converter
Prj141 Digital Interface
Prj141 Software
Prj141 Filter Design
Prj141 Filter Evaluation
Prj141 LX9 Utilization
Prj141 Higher Sampling Rates