Prj141 - DDC Digital Block (Part 3)

Following on in the walk through of the Spartan LX9 with ADC and BBB, after the Signal Processing Block is the digital interface block.  The basic approach was not changed from the first digital testing approach here, however, lots of practical items were incorporated based on lessons learned during the rest of the development.  A block diagram of the digital interface and control is shown below.

DDC Digital Control and Data Interface

The digital control block is clocked by a 48 MHz digital clock from a DCM originating from a 12MHz clock (generated on the XuLA2 board for its USB programming interface).  While the sample clock could be used, this allows the digital section to work without the sample clock being present (partially populated boards or boards with defects).  The ADC sample clock is provided to the digital section for counting and in diagnosing newly fabricated boards.

The SPI interface represents a separate and asynchronous clock domain.  It is driven by SS and SCLK from the host computer.  It latches SO and SI at the start/end of being BSY, where BSY is determined by the SPI  SS and SCLK count. 

The port controller is a finite state machine which starts when the SPI stops being busy.  At this point the SI or serial input word just received is parsed and acted upon.  The lower 4 bits of this word determine which port (0 or 1) will be read (or written).  In the case of a write the FSM take the upper 12 bits of the serial input word and writes them to the appropriate port.  For a read, the FSM reads 16 bits from the specified port and latches them into SO or the serial output word for the next SPI transaction.

For simplicity port 0 is always connected to register 0.  This register has a couple of light weight controls and status.  One of the key sets of bits in register 0 is the P1 selects bits which determine which register is currently connected to port 1.

The register definitions are fully specified in the VHDL top level readme.txt.  The key registers are R0(control previously mentioned), R1 (FIFO data), R3 (Fifo source select and test pattern generator control), and R6/R7 (PINC or frequency control of signal block NCO/DDS local oscillator). 

The other registers are utility registers used to debug and test boards, software or VHDL.  I must admit I under estimated the need for and value of these.  The firmware version is available to keep your sanity and make sure you programmed the image you thought you did.  The sample clock counter lets the software test to see if there really is a valid sample clock present (and you can expect any FIFO samples).  The digital clock counter is a good simple internal test available to the software interface along with the counter on the number of port 1 reads.  Like-wise the LED outputs on register 0 allow basic simple scripts to check a board and firmware for SPI connectivity.

Related:
Prj141 Schematic
Prj141 Overview
Prj141 Digital Down Converter
Prj141 Digital Interface
Prj141 Software
Prj141 Filter Design
Prj141 Filter Evaluation
Prj141 LX9 Utilization
Prj141 Higher Sampling Rates