Tuesday, December 24, 2013

A-B Board SDR

The mixer and amplifier sections of the B board were populated.  The amplifier supply was errantly captured in the schematic as +3.3V and should have been +5V.  A trace cut and white wire corrected this.  A 19 inch 30AWG wire attached to an SMA served as a simple antenna.  There are no image rejection filters and no low noise pre-amplifier.  This leaves the noise figure no better than the first stage BGA2866 amplifier at ~3.8dB and doubles the mixer NF by allowing the image noise.  All things considered this is working quite well.

The following video captures using the A-B board combination with SDR-Console (previous SDR captures used an external LNA and down converter with the A board only).  The console has not been calibrated in dBm so only relative comparisons are valid.  Several local broadcast FM stations are covered including their RDS and demodulated FM spectrum.  In addition, the local narrow band NOAA weather broadcast is shown.  The upper left xterm is a "top" session running on the BBB showing CPU use (the radio application is dev-pru).  The lower left xterm is the console output of this application.  The running output is the complex sample rate.  The ADF4351 programming debug is also enabled and visible on tuning change.

video

Sunday, December 22, 2013

B Board synthesizer construction

The first B board was populated incrementally.  Previous experience had shown the QFN32 (or similar) packages to be challenging to properly solder, at least for me.  To help with this in the layout the center pads were shrunk to avoid shorts with the outer pads, and the outer pads extended out significantly.  The pad extension has several effects: a) it provides a better overall visual alignment queue, b) it provides a reservoir for solder, c) it provides additional re-work and alignment space.  While this will impact device performance, the apparent alternative is to not use the part or pay to have boards populated (both of which defeat the point of the exercise).  

Below is a picture of the synthesizer portion populated (along with the DFN8 mixer which air gunned at the same time as the ADF4351 and TCXO).  It is mounted on a previous build A board (ADC IF) which in turn mounts on a Beagle Bone Black.
The ADF4351 (U104) is left center just to the right of the TCXO. 

Beagle Bone C/C++ software using the GPIO sysfs interface was developed to configure and monitor the devices including lock detect indicator.  The following are spectra of the aux output using lowest power level at 100, 300, 500, 700, and 900MHz.  The display is from a 7L12 (1973 vintage, user calibrated - I'm on a budget).


100MHz Aux Output


300MHz Aux Output

500MHz Aux Output
700MHz Aux Output
900MHz Aux Output
The 7L12 limit is 1500MHz and the output is similarly clean to that limit.  Below is the schematic of the board as ordered and built thus far.

131212 B Board As-Ordered Schematic



B/C Boards Overview


1                   B/C Board

The B and C boards share a common PCB and differ only in population and configuration.  They mate with an A board which provides BBB connection (the additional space taken by the BBB dual row headers is needed).  The board provides a wide band synthesizer, mixer, gain block, and input filter.

1.1         Architecture

The module architecture is as follows.

1.1.1        Power and Misc

The board uses the BBB system 5V from the A-board.  Two low noise 3.3V regulators are used, one for the synthesizer (due to its high power consumption), and one for everything else including output drive.  An I2C eeprom is include to store the device tree for the cape and allow automatic probing of the board.  Due to space, fixed SMT resistors are used for board identification rather than a DIP switch.

1.1.2        Filters

There are filters on the PCB.  The first is a bandpass GPS SAW filter (1575.42MHz center, 2MHz bandwidth). By default this filter is populated in the C-Board configuration.  The second filter is a 3rd order low pass LC filter which can be configured by the user. By default, it is configured as a 1500MHz LPF in the B board configuration. Both are terminated in 50 ohm inputs and outputs.

1.1.3        Amplifiers

A single stage fixed wideband +20dB amplifier is used. It has a noise figure of 3.8dB and is specified from DC to 2.2GHz.

1.1.4        Active Mixer

An active wideband mixer is used.  It is a low power and low cost device used in an unbalanced input and output mode to avoid the cost and space of wideband transmission line transformers. The package is a DFN8.  Unfortunately, most high performance RF parts are only available in lead-less packages.  Care has been taken in layout to provide ample space surrounding the part for alignment and re-seating if necessary.  Based on previous experience with hand construction involving QFN/DFN parts, the pads have been extended to provide solder paste channels and unaided visual alignment guides.  While this may reduce the overall performance, the alternative seems to be to not use the parts or suffer with high fall out rates of hand built units. 

1.1.5        Wideband Synthesizer

A dual output wideband synthesizer (37MHz to 4400MHz) is included.  One output is used to differentially drive the active mixer while the other is made available via a SMA output.  The auxiliary output is resistively terminated and single ended output, again to provide a wideband response while avoiding the need for wide band transformers.  The serial control interface is implemented via GPIOs from the BBB, through the A-board.  A common SDAT, SCLK is used for all boards.  The serial chip select (CS) and lock detect indicator (LD) are assigned to different GPIOs based on B/C board type to allow both to co-exist with an A-board.

Objective


The goal is to create a set of low cost experimentalist RF modules to be used with the Beagle Bone Black and a PC.  The focus is on simplicity, experimentation, and hand constructible modules.  Large or expensive FPGAs and ADCs are avoided.  A significant goal is to provide a relatively easy platform to explore advanced topics in signal processing and RF while leveraging existing software packages.

Three boards partition the functionality.  Each board is useful on its own and is suitable for hand construction and modification.  The following illustrates some of the basic configurations.



A Board Overview


1                   A-Board / Prj123

The A-board is a 12 bit, <3 MSPS ADC board with anti-aliasing filter. (Sometimes this is also referred to as a Prj123 board).  The sampling rate is configurable to common Ethernet SDR frequencies to support use with several SDR software packages.  Two stages of configurable gain are provided.  A 10.7MHz ceramic filter is used for anti-aliasing while provisions are made on the board for a user defined 3rd order bandpass LC filter.  Serial data is pumped out of the ADC using the BBB PRU.  Conversion from real to complex samples is done within the BBB ARM processor.  The BBB 100MB/s Ethernet is used to transmit samples and for control of the board set.

1.1         Architecture


The basic top level architecture is shown below.

1.1.1        Power and Misc

The board uses the BBB system 5V input with a single low noise 3.3V regulator.  An I2C eeprom is include to store the device tree for the cape and allow automatic probing of the board.  Due to space, fixed SMT resistors are used for board identification rather than a DIP switch.  Two 2x5 stacking headers are provided to allow mixer/amplifier/synthesizer/filter boards to be stacked on top of this board.  This allows those boards to recoup BBB cape space which would be used by Ethernet connector cut out and the P8/P9 connectors running the length of the board.

1.1.2        Filters

There are two anti-aliasing filters on the PCB.  The first is a 10.7MHz ceramic filter with 330kHz 3dB bandwidth.  It is input and output matched to 300 ohms (input via C101 and L101, output at first stage amplifier input).  The second filter is a 3rd order bandpass LC filter which can be configured by the user. The ADC uses sub-sampling or Nyquist wrapping to sample a narrow bandwidth, determined by the sampling rate, of a higher frequency IF.

1.1.3        Amplifiers

Two stages of amplification are provided.  The second stage is primarily to buffer the ADC but does provide gain.  Each stage is implemented using a high bandwidth OpAmp (U109, U111).  Two gains are dynamically configured via GPIOs to a MUX selecting the feedback resistor on the inverting input.  Each OpAmp uses an independent virtual ground and is AC coupled to accommodate independence and modification.  In the case of lower desired gains (e.g. for large signal instrumentation applications), compensated OpAmps should be used.

1.1.4        ADC

The ADC used is a 3MSPS single ended input with a 55MHz half power bandwidth explicitly chosen for sub-sampling application and cost.  It uses a standard serial interface with the sample clock being the chip select. (the BBB SPI interface was attempted, however, it is not suitable for this purpose given the jitter on the serial CS even in FIFO mode).

1.1.5        Sample Clock Generation

One of the more subtle aspects of the A-board is low phase noise sample clock generation.  Earlier versions of the board used the BBB PWM output as the sample clock.  While this produced reasonable phase noise, it is not sufficient for most RF work (It is quite good considering the BBB intended application, indeed, A-boards can be modified to use this and achieve a wide range highly configurable sample clock.  Sample clocks in excess of 2MSPS have been used).  The summary of sample clock generation is that a 20MHz TCXO is divided by 12, 16, or 4.  The clock divider value is set via GPIOs.  This clock is provided to the ADC as well as the PRU (to be used in triggering serial clocking out of the data).  The divided 50% duty cycle clock is AND’ed with a PRU output to generate the actual ADC sample clock.  This allows the PRU to “hold” the next sample clock edge to achieve different sampling rates.  Given the PRU’s fixed instruction cycle of 5nS, good control of lower sample rates is achieved. (the falling edge drives the sampling process and has the low phase noise of the divided TCXO).

1.1.1        PRUs and CPU

Processor performance is another subtle aspect of the design. PRU0 controls the serial transfer of sample words from the ADC.  These are placed in SRAM where PRU1 extracts them and stores to DRAM where the processor can access them.  For higher sampling rates it is necessary to use the second PRU as the DRAM interface rather than having the first PRU deal with variable and large memory latency and the ADC serial interface.  The ARM processor extracts the real samples from DRAM converts them to complex samples via Fs/4 mixing and low pass FIR filters (Hilbert transform logical operation).  This is done using 32 bit signed integers to offset the ARM floating point performance (software emulation). IP packets of complex samples are then sent to the network.

1.2         Software

There are three primary components in the software used. Those are the BBB low level software, BBB application servers, and the PC applications which interface to the BBB.

1.2.1        BBB Low Level Software

The first utility is pructl.  This tool loads the images for the PRUs and provides debug and diagnostic information regarding the state of the SRAM and DRAM sample fifos.  The second set of utilities are scripts to set the gains of the IF amplifiers and select the clock divider value.  All of these are user space utilities written in C/C++/Bash scripts.  The only required kernel module are the pruss driver for the PRU, and GPIO driver, both of which come configured within the default BBB kernels.  The HDMI portion of the device tree must be configured out of BBB to use some of the io pins.  This involves a one-time configuration of the kernel boot arguments and is well documented on the BBB wiki.

1.2.2        Application Servers

The application servers are user space Linux processes and required no additional kernel modules.  They are written in C/C++ and require no additional libraries or software packages beyond those included in the default BBB Linux distribution.  A single process uses multiple threads to provide an ASCP (amateur station control protocol) interface, a human usable command line interface (accessed via telnet’ing into the process from any host on the network), and an ADC test and evaluation tool interface.

1.2.3        PC Applications

The PC applications fall into two categories: open source / publically available SDR packages (i.e. CuteSDR, SDR.com) and small custom java applications used for test and specialized instrumentation purposes.