First the primary SPI software is a function of the F board and was developed for multiple projects. This software provides a SPI cpu C++ and PRU interface. The former toggles the SPI lines directly via Beaglebone black gpios while the later sends commands to PRU0 which toggles the io lines to the fpga. The advantage is that the later can achieve SPI clock rates in the 9 – 16 MHz while the former is limited to kilohertz range.
The second interesting aspect is that the basic digital control block of the VHDL image not only provides registers to control the signal block and quadrature down conversion but also two ports of 6 pin gpio. These ports can be used simultaneously by other boards and their controlling software. The software needs to provide an independent mechanism to access these ports while not significantly impacting streaming of IQ ADC streams.
The final aspect of interest is that the down conversion software on the Beaglebone Black provides a standard IQ ADC interface to other software applications . In the cases where the 40MSP and 4MSPS channels are selected the cpu cannot process the full set of streaming data. In the case of the 200kHz channel (2 bytes/sample or 400kB/s) the processor can stream the channel to a network SDR application.
To address the above considerations, the software was structured along the lines of the following diagram.
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| Software Organization |
Starting at the bottom, PRU0 controls the SPI pins to the FPGA. Based on simple throughput measurements the PRU can drive a SPI clock of ~ 9MHz driving 1x SPI width. This results in ~515 kwords/second measured (with a word being 16 bits). The 2x SPI would give slightly less than 2x performance (due to additional instructions for manipulating two bits at a time). PRU0 has two command mail boxes in its SRAM which it monitors. They are serviced round robin. Each command contains an operation, a number of words/bytes, and the words/bytes to transfer. As the words are shifted onto the SPI interface, the values shifted in are placed in the SRAM mailbox. One mail box is used by the CPU to request SPI transfers while the other can be used by PRU1.
BDC
The CPU interface SpiXferArray16 is used by the BDC software to read and write 16 bit registers. The writes can occur in a SpiXferArray16 of length one, while reads require two operations. Register reads are conducted this way so that a read command (command in first word, and results obtained in second) are not split across transfers done by the PRU1 (or visa versa). The BDC software SpiRead16/Write16 is used by the QDC100 software to configure the quadrature conversion as well as the gpio ports implemented by the BDC software.
Tboard , Mboard , DDC/QDC
The BDC gpio interface is used by the user space I2C (UI2C) software to support the devices on the T board (MAX2112 tuner, and MCP4725 DAC for variable gain amplifier), while the BDC gpio interface is also used by the SPI interface within the ADF4351 control software used by the M board (synthesizer section).
Concurrent with all of the above operations PRU1 under the control of the QDC100 software continuously requests PRU0 to conduct SPI read operations to the FPGA. These operations are: a) read fifo samples in sets of 256, and b) read the sample fifo threshold register to ensure it is not empty (and can safely be read). PRU1 places the samples it streams from the fpga fifo to a DRAM circular buffer shared with the cpu. The QDC100 Get2kSamples() interface extracts those from the DRAM buffer and provides them to the calling application.
Other interfaces are present at all horizontal lines and not shown for clarity (e.g. the QDC100 provides an interface to select the channel to be streamed through the fifo and the digital downconversion frequency, the M board provides an interface to set the LO frequency, and the T board provides a tuning frequency for its LO, rf and baseband gain settings and baseband filter cutoff frequency).
The above structure allows each of the pieces of software to support various environments and configurations while at the same time maintaining device independence and allowing concurrent operation and control of the devices.
Related:
Prj 146 - Dual Channel 40MSPS ADC (Part1)
Prj 146 - VHDL for Quadrature Downconverter (Part 2)
Prj 146 - C++ Device Software (Part 3)
Prj 146 - Dual 40MSPS ADC Kicad Source Files
Prj 146 - Quadrature downconverter VHDL
Prj 146 - Device C++ Software
Prj 145 - Beagle Bone Black Simple LX9 FPGA board (Part 1)
Prj 145 - BBB LX9 C++ and VHDL (Part5)
Prj 141 - Spartan6 LX9, ADC, and BBB (Part1)
Prj 146 - VHDL for Quadrature Downconverter (Part 2)
Prj 146 - C++ Device Software (Part 3)
Prj 146 - Dual 40MSPS ADC Kicad Source Files
Prj 146 - Quadrature downconverter VHDL
Prj 146 - Device C++ Software
Prj 145 - Beagle Bone Black Simple LX9 FPGA board (Part 1)
Prj 145 - BBB LX9 C++ and VHDL (Part5)
Prj 141 - Spartan6 LX9, ADC, and BBB (Part1)
