10MSPS ADC with a BeagleBoneBlack

I wanted to revisit the ADC board used previously with a BBB for SDR and instrumentation work. The first version used a serial ADC with a PRU.  It produced acceptable SDR results (and here and here )  However, for instrumentation work the SFDR was less than desired due to amplifier selection (saga described here).

The first goal was to increase the sample rate without resorting to an FPGA.  Previous measurements and benchmarks indicated that 10MSPS should be possible.  Additional bits of resolution was also a goal.  Most serial ADCs at 14+ bits do not have sample and hold bandwidths high enough for use in the intended subsampling application.  In addition, getting to just 2.5MSPS using a serial interface is challenging using only a PRU to clock the data. I decided to start simple and use a parallel part with a differential input.  The LTC2225 was selected as it supports the desired sampling rate, has a large SH bandwidth, is reasonably priced, readily available, and has a 12 and 14 bit variants.

Another goal was to stack the new ADC board with an existing IO board thus allowing a single BBB to control mixers, gain and filter boards.  The led to PRU1 being used to interface with the parallel ADC.

The following is a block diagram:

BeaglBoneBlack 10MSPS ADC board

There were some errors and difficulty involving the power on reset circuitry (PRU1 R31 uses pins that are shared with the system boot mode selection).   The following is a picture of the updated and functional assembly (white wires and all).  Given the changes I will post a schematic once the PCB has been updated.

10MSPS ADC mounted on BBB.
TCXO upper left, LTC2225 upper right, LTC6406 bottom right, regulator and power-on circuitry lower left.

Even though it can't be stacked yet, its good enough to take some measurements and work on the software for higher sample rate processing.

Interface Board Updates

An interface board was developed to provide 3 ports of 6 discretes and +5V in a 2x5 header connector.  It also allows high side switching of the +5V supply. The first version is described here. I did not properly check the power-on state of the enable gpios. I also realized that I should have buffered all of the pins.  Most digital IOs have ESD protection diodes.  What this means is if you are not careful, a digital high voltage can partially power the part when the main supply is switched off.  This has the negative effect of raising a pin above VDD (which is ~0) and can damage the part.  The software worked around this by ensuring that when the supply was disabled all IO pins were at 0.  I took the opportunity to correct this and add a FET buffer between the BBB gpios and the connector pins.

There was one error on the board where the inputs to an inverter were swapped (NC was connected to the input).  By using a NOR gate in the same package rather than the inverter I was able to correct this without a white wire.  The schematic is shown below.

There is one pin unused (PRU1_R31_15) on the P9 connector to allow stacking with a board using the rest of the PRU1 pins on P8.