The first goal was to increase the sample rate without resorting to an FPGA. Previous measurements and benchmarks indicated that 10MSPS should be possible. Additional bits of resolution was also a goal. Most serial ADCs at 14+ bits do not have sample and hold bandwidths high enough for use in the intended subsampling application. In addition, getting to just 2.5MSPS using a serial interface is challenging using only a PRU to clock the data. I decided to start simple and use a parallel part with a differential input. The LTC2225 was selected as it supports the desired sampling rate, has a large SH bandwidth, is reasonably priced, readily available, and has a 12 and 14 bit variants.
Another goal was to stack the new ADC board with an existing IO board thus allowing a single BBB to control mixers, gain and filter boards. The led to PRU1 being used to interface with the parallel ADC.
The following is a block diagram:
|BeaglBoneBlack 10MSPS ADC board|
|10MSPS ADC mounted on BBB. |
TCXO upper left, LTC2225 upper right, LTC6406 bottom right, regulator and power-on circuitry lower left.