Friday, August 22, 2014

A board SFDR

After some more thinking about it, things weren't adding up with regard to the harmonic levels seen by the ADC on the A board.  To better investigate the harmonics at the ADC,  I decided to create an external 2x cascaded 10.7MHz ceramic filter to use with the signal sources I have.  The following is a spectrum of a cleaned up 10.720 MHz source.
0 to 50MHz capture of 10.720 MHz filtered source.
This signal is -34dBm with no harmonics or noise above -90dBm.  It is based on an Si570 from older projects and has a different spectrum footprint than the ADF4351.  It was applied to unit #2 A board (lower IF gains).  Using the raw ADC capture application within the workbench tools in google code, the following ADC spectrum was obtained.
10.5MHz to 11.0MHz capture of 10.720 MHz filtered source.
The sampling rate is 1MSPS and undersampling is used to obtain a capture of the 10.7MHz signal.

A 10.720MHz input will alias to 11.00 – 10.720 MHz = 280kHz and is shown at marker 1 at -35.9dBref (recall that 10.5MHz is on the right, while 11.0 MHz is on the left).  The second harmonic of the input at 21.440MHz will alias to 21.000 – 21.440 = 440kHz which can be seen at marker 2 at a level of -76.8dBref  (Again, 21.0 MHz is on the left, while 21.5MHz is on the right).  This indicates a level difference between the fundamental and second harmonic of 76.8 – 35.9 = 40.9dB.

This is consistent with older harmonic measurements.  I had previously attributed them to the high harmonic content from the mixer and only 40dB of stop band rejection in the anti-aliasing filter, however, given the source used here that is clearly not the problem.  A quick review of the ADC datasheet showed -80dBc SFDR (unaliased, and its not clear to me how to translate this to an undersampling application).   Focus them turned to the OpAmp's used for the ADC buffer/amplifier.

The following is a graph from the ADC interfacing OpAmp using a +5V supply.
The part is used with this gain and closer to a RL=100 ohm.  While the outputs in the measured data above are not 2Vpp, I am using the part at 3.3V.  The same graph for the first OpAmp stops at 5MHz.  In short, I could have done a better job on OpAmp selection for the application.

My first intention was to rework one of the existing boards with a better part.  Unfortunately I painted myself into a corner.  The foot print is a standard SOIC8.  When you couple this footprint with 3V uni-supply operation and the desired SFDR you quickly reduce the options.  In addition, it gets pretty pricey for having two stages of programmable gains provided.

Given all of this and the fact that there are several things I have been hoping to revisit on the ADC board (simpler clocking structure, higher speed parts, higher resolution parts, ...)  I'll hold off on rework and focus my time and energy on an updated board.

Monday, August 11, 2014

Single Stage Conversion Spurious Responses

In the three stage conversion there were multiple spurious response noted.  Rather than trying to understand them with 3 mixers and LO's I decided to back up to a single stage, pull out the Analog Devices PLL simulator and account for what I was seeing.

The basic test configuration uses a Prj114 source set at 500MHz.  This is an integer multiple of the PFD frequency of the PLL so it should generate no fractional spurs.  I have not been able to observe integer or reference spurs in any of my measurements so I was not concerned with them.  In addition, the Analog Devices ADIsimPLL output indicates their level should be negligible with my particular configuration. The single stage conversion is set with a LO of 510.75MHz nominally.  This is a fractional setting and should generate fractional spurs.

Just to get oriented, a 100MHz span was taken at the mixer output using an SA0314 to see what was going into the A board.  That spectra is below.
While the RBW is large, the IF harmonics are quite clear and quite large.  Using this signal, the ADC application was used to capture the ADC results.  These are not in calibrated units but are in dB relative to a full scale ADC value.
After a fair amount investigation, the discrete spurs here appear to be IF harmonics.  The ADC filter only provides 40dB of out of band attenuation.  The harmonics are high due to using the mixer in a single ended configuration.  Even in a 3 stage conversion where the last LO is fixed, the input signal can have energy within the pass band IF that when a harmonic is applied, the result alias and end up near the non harmonic. Basically, a better mixer design and ADC filter should address these.

So we put aside the IF harmonics and focus on the near in phase noise of the IF (and consequently fractionally generated LO).  The ADIsimPLL results for this synthesizer setting are shown below.
ADIsimPLL results for 510.75MHz synthesis, low-noise (dither off), divider outside PLL loop, 35kHz loop bandwidth
Based on this I would expect a smearing due to spurs about 60dBc out to at least 30kHz.  Using the ADC results (same data as in previous ADC figure)  and looking only at 30kHz about the carrier we see:
While the spurs are not discrete, the lobe off the carrier does rise to -60dBc and roll off from there and is in the range of expected spurs.  I am actually quite happy with these results and being able to account for them.  There are several options to reduce the close in phase noise including using the dither option on the ADF4351 or using integer synthesizer configurations in the second and third stage down conversions.  However, compared to the spurious responses due to the mixer IF harmonics and ADC filter the close in phase noise is a topic for a different day.