Wednesday, July 20, 2016

Prj 146 - VHDL for Quadrature Downconverter (Part 2)

This post walks through a VHDL application for quadrature down conversion on a dual channel 40MSPS ADC. A previous project constructed a digital down converter with a single real input channel and CIC filters and decimators with compensation filter in a LX9.  For this project I wanted to do something similar but not use CIC filters and provide multiple stages of down conversion to allow variable bandwidth sampling.  The following is a block diagram of the VHDL image - referred to as QDC-100.  All of the VHDL discussed is here.
QDC-100 Summary Block Diagram
The digital control portion of the FPGA image is the BDC block described here.  It provides the SPI interface to the BeagleBone Black along with control and status discretes to the signal processing block. Internally it executes at 96MHz (using the DCM). All of the sample data from the signal block is transferred via a fifo and all of the control information to the signal block are discretes.
QDC-100 Signal Block Summary
The channel match and test block provides  a mux to select the actual ADC samples or a test signal and equalize the channels to compensate for DC bias and gain differences in the analog front end.  The mixer and LO stage is just as it sounds, a numerically controlled oscillator or QDC which is complex multiplied by the input signal.  The decimators are two stages of filter and decimate to bring the sample rate down to a manageable level.  Two stages are used to provide different bandwidths and reduce the filter requirements.  The final stage selects samples from any of the previous stages and writes them to a fifo in I/Q 16 bit signed format for extraction by the digital control block.  The fifo provides a minimum number of samples (2048) indicator and a flush/reset control.

The following is a block diagram of the channel match and test pattern generator section.
QDC-100 Channel Match and Test Pattern Generator
The test pattern generator creates a I/Q signal with a known level using a small DDS (8 bit phase, 12 bit output) and a shift right level control (0dB, -6dB, …).  The ability to use a known digital high quality signal is extremely helpful in testing the rest of the design.  If the TPG value is 0 the muxes select the ADC data, otherwise, they select the test pattern and the test pattern is determined by the TPG value.  The output of the muxes  for each I and Q channel is then run through an adder and divider to remove the DC offset bias and equalize the amplitude of the channels.  Removing the DC bias removes down stream carrier products of the subsequent mixer and equalizing the amplitudes (removing channel gain variation) reduces down stream images.  The gain equalization is accomplished by multiplying the signal by an 8 bit signed value and then selecting the high bits of the output.  This has the net effect of multiplying the signal by N/128, where N is the Inum or Qnum.  This allows small variations to be matched with essentially the higher gain signal being reduced by a small fraction.  Using a signed quantity has the added benefit of being able to switch the I/Q channels.  If we use a –N value for one channel it shifts the channel by 180 degrees.  If that channel lagged the other by 90 degrees, it now leads it by 90 degrees thus swapping I/Q.  The outputs are 12 bit I and Q values which have been equalized.  The entire block works on a sample clock basis.

The following is a block diagram of the mixer and LO section.
QDC-100 Mixer and Local Oscillator
This block is relatively straight forward and uses a Xilinx DDS and complex multiply generated cores. The DDS block generates an in phase (12 bits) and quadrature (12 bits) sinusoid which is fed to the multiplier.  The multipliers output is two 16 bit values (I and Q) and routed to subsequent stages as a 32 bit vector.   Since the PINC bits are a set of discrete lines from another clock domain, a small state machine – the AXI Slave writer monitors for values changes and writes the phase increment register of the DDS core. Again, the entire block works on a sample clock basis.

The following is a block diagram of the decimator section.
QDC-100 Two Stage Decimation
There are two decimator blocks.  Each operates on 16 bit inputs and outputs and has its own internal clock.  The decimators are Xilinx generated cores and include a FIR filter applied prior to the decimation.  The first filter decimates by 10 and the second by 20.  The following is a block diagram of a decimator block.  Both A and B are structurally the same with the differences being the decimation rate, filter applied, and internal clock rate used.

The following is an internal block diagram of a single decimation stage:
QDC-100 Decimation Stage Internals
Each decimator uses an independent filter clock derived from the sample clock.  A DCM is used to generate a filter clock multiple times the sample clock (e.g. from 40MHz to 200MHz).  Each decimator has input and output fifos with independent read and write clocks.  This isolates the higher frequency filter clock domain.  The higher rate filter clock allows a smaller number of DSPs to be used to generate a FIR filter and decimator with a larger number of taps than would be possible using a filter clock at the same rate as the sample clock.

The signal block output is simply a fifo.  The input to the fifo is a 32 bit wide interface (16 bits I, 16 bits Q), while the output is a 16 bit wide interface.  This takes advantage of the Xilinx generated fifo capability to have different input/output widths.  This allows single cycle writes of I and Q data during a single sample clock while allowing the digital processor interface to retain a 16 bit wide register/fifo read interface.  The following is a block diagram of the output.
QDC-100 Signal Block Sample Output to Digital Block
The mux select determines what gets written to the fifo.  Output from any of the stages or processing can be selected.  The input fifo clock is the sample clock with the write valid always being true for non-decimated inputs or the valid signal from the decimators.  The output fifo clock is the digital control clock with the read enable driven from the digital control register read block.