Tuesday, September 29, 2015

FPGAs and VHDL on a budget

The Beagle Bone Black (BBB) and its PRU go a long way to building non-trivial projects (e.g. all of the boards in gallery1 and gallery2 including a  Level controlled RF synthesizer10MSPS ADC, and multistage SDRs.)  Having a simple, flexible, low-cost FPGA available started to become very appealing.  In looking around at various FPGA boards the XuLA2 Spartan6 LX9 caught my attention for several reasons. First the pin out is extremely simple (40 pin DIN at 900x100 mil spacing), second it has enough IO pins to be usable with ADCs, DACs, and an SPI but not so many as to be cumbersome, third it includes an SDRAM which could come in handy, and finally the cost is low enough that I could afford to purchase multiples and not worry about loosing one due to mistakes on the bench.
The near term goal was to interface the FPGA to an ADC and a BBB and the longer term goal being to eventually incorporate an NCO, digital mixer and filters.  I am also not a VHDL expert so things needed to progress incrementally.  Given this, I created a simple board as a carrier for the XuLA2 that included an SPI interface, LEDs and an ADC.  The schematic of that board is below.
XuLA2 and ADC carrier board schematic.
The idea is that there is enough on the board to develop and test an SPI interface and then populate the rest of the board with a 12 bit ADC.  The ADC and sample clock oscillator are pin compatible from 10MSPS up to 66MSPS (depending on how much you want to spend and can use).  Below is a picture of the first unit partially populated with only LEDs, SPI interface, and XuLA2. It is connected to a BBB via an SPI interface using the GPIOs through an Beagle Bone Black interface board.
Beagle Bone Black with interface cape at left.  XuLA2 w/ Spartan 6 LX9 on ADC carrier on right.

The first FPGA image developed included an SPI interface with an internal control register and a couple of counters (block diagram below).
Block diagram of VHDL for LX9 digital interface.

The SPI block serializes data into SI and out from SO.  The port controller is a finite state machine that uses the SI as a 16 bit command. The low 4 bits specify whether the transaction is a read or write and which port to read and write from while the upper 12 bits serve as the data.  Reads and writes with port 0 always go to register 0 (R0).  This is the primary control register which includes settings for the LEDS, ADC sampling enable and selecting what hardware is multiplexed to port 1.  Reads and writes with port 1 can be to a secondary set of control registers (R1 and R2), a set of counters, or a FIFO which crosses the system clock and ADC sample clock domains.  The overall programming model then becomes writing a command (and reading the results from the previous command since the serial data is clocked out concurrent with clocking in the write data).  For streaming operations, the port 1 selector is first configured to connect to the FIFO and then a stream of read-port-1 commands are issued.

This approach worked well.  It has enough complexity to serve as a non-trivial, applied learning exercise yet is simple enough to be tractable to debug without lots of test equipment and tools.  The SPI programming can be easily driven by and changed in the BBB user space C code. This means you can slow down transactions to seconds and verify things on the target hardware with the LEDs. The counters allow pattern verification of reads at all speeds and check the integrity of the interface.

Prj141 Schematic
Prj141 Overview
Prj141 Digital Down Converter
Prj141 Digital Interface
Prj141 Software
Prj141 Filter Design
Prj141 Filter Evaluation
Prj141 LX9 Utilization
Prj141 Higher Sampling Rates

HTML5 Canvas Experiment

After having completed the simple html/css/javascript synthesizer application (described in Part1Part2Part3, Part4) I wanted to evaluate using an HTML5 canvas for an instrumentation like display.  There are lots of good graphic packages available, however, I did not find one that seemed to offer basic and simple xy plots suitable for what I wanted to do with a browser based instrument.  For me the real keys were: a) simplicity where I could understand the code and tailor it, b) ability to graph 500 – 2k work of xy points every 50mS or so, c) basic measurement things like envelopes, memories, peak picking, a cursor, and markers.  Given this and the desire to spend a little more time advancing my javascript comfort level with non-trivial examples I decided to build a simple version of a similar Java display I have used (illustrated in the posts on ADC and spectrum analyzer experiments).

The package was developed as a standalone file with a couple of test drivers.  The tests themselves run in the browser and require no back end server to drive them.  The source code is at BREC/Js and a browser executable demo is here.  An image of one of the unit tests is below.

Example of HTML Canvas used to graph signals.  Browser demo available here.
The example has several buttons along the bottom.  The "run" button causes internal updates to the XY sequence displayed.  In the default case this is just a sinusoid with a up and down chirping frequency.

The "marker" button displays 10 markers.  These start out as predefined values on a sinusoid.  If you click anywhere on the canvas, marker 9 moves to that position.

The "peaks" button toggles peak picking.  When peak picking is on, markers 0 - 8 are taken over and assigned automatically to peaks found.  Marker 9 still follows the last canvas clicked location.

The "memshow" button toggles the display of a XY sequence in memory.  This is shown in light blue. The "mem" button captures the currently displayed sequence into the memory.

The "envelope" button toggles an envelope history.  When enabled the envelope is initialized and displayed.  When toggled off the envelope is hidden and not active.

The "function" button toggles between two internally generated XY series.  The first is the chirped sinusoid, the second is a spectrum like signal with two peaks and some random noise.

Saturday, September 12, 2015

Browser controlled synthesizer (Part4)

The fourth step in constructing a simple webpage controlled RF synthesizer is the mechanical assembly and packaging. (The previous steps are described in  part3part2, and part1)

Originally I had visions of constructing shields on the boards in RF sensitive areas and packaging the entire setup in a nice professional small case.  Let’s just say I’m learning…  Rather than getting hung up on the difficulties and errors in this regard I decided to forge ahead.  All I really needed was a dust cover.  The real concern is just protecting the electronics from having a tool fall on them or more likely a SMA connector brush across them as the cable flips over unexpectedly while reconfiguring a setup. To this end I decided to use some scrap plywood and acrylic.  The plywood provides enough mass that the instrument doesn’t get dragged around on the bench with cable tension and is sturdy enough that you can stack things on top of it.  Granted, it provides no shielding and I’m not entirely sure of the ESD properties.  Same for the acrylic face plate.  The face plate is thin enough that you can get the connectors through it and you can at least see the LEDs to know if it is powered on and should be working.  The following are a couple of pictures of the assembly. 
BBB Browser Controlled RF Synthesizer on Mounting Plate

Synthesizer with dust cover
The example below captures the control panel during a sweep along with the measured spectrum.
Browser based control panel.  Sweeps from 37MHz to 67MHz (1MHz steps) and from 0dBm to -30 dBm (1dBm steps).  At the time of capture the output at that steps was at 50MHz/-13dBm.

Spectrum of output.  There is a 30dB pad between the generator and the analyzer.  You can see the 3rd harmonic of the low frequency portion of the scan on the far right near 74MHz.
Similar sweeps and single frequency outputs are achievable through 2GHz.  Beyond this point the amplifiers used start to lose gain and the level drops and level control is reduced.  The following captures a sweep across 1.4GHz - 1.5GHz in 5MHz steps.
Constant level sweep from 1400MHz - 1500MHz in 5MHz steps.  Output at -5dBm with 30dB pad between analyzer and synthesizer.