The basic test configuration uses a Prj114 source set at 500MHz. This is an integer multiple of the PFD frequency of the PLL so it should generate no fractional spurs. I have not been able to observe integer or reference spurs in any of my measurements so I was not concerned with them. In addition, the Analog Devices ADIsimPLL output indicates their level should be negligible with my particular configuration. The single stage conversion is set with a LO of 510.75MHz nominally. This is a fractional setting and should generate fractional spurs.
Just to get oriented, a 100MHz span was taken at the mixer output using an SA0314 to see what was going into the A board. That spectra is below.
So we put aside the IF harmonics and focus on the near in phase noise of the IF (and consequently fractionally generated LO). The ADIsimPLL results for this synthesizer setting are shown below.
|ADIsimPLL results for 510.75MHz synthesis, low-noise (dither off), divider outside PLL loop, 35kHz loop bandwidth|