Saturday, January 17, 2015

ADC Measurements

Before taking any meaningful measurements with the 10MSPS ADC board I took the time to update the software.

Software Updates

The BBB PRU software was updated to normalize the data samples to 16 bit unsigned.  Unfortunately, the 2 most significant bits from the ADC are not accessible on this board (During design, I went back and forth with the 14 bit version and in one of the rounds of updates shifted the data lines wrong). This has two implications.  First I cannot use levels higher than quarter scale or -12dBFS. Second it also means there is some bit manipulation required to make the quarter scale values come out correctly.  I also took the time to factor out multiple PRU images to support programmable down sampling or filtering images.  To support this I optimized the benchmark software a little to recoup a few instructions.  The basic difference is that spinning waiting for clock transitions is done using a quick branch bit test and the communication of the sample fifo pointer between PRUs is done using a XIN/XOUT side transfer instruction rather than SRAM accesses. (source code is under the H board directory or here ).

The PC analysis software was updated to better handle the higher sample rates. The tools I used were developed over time with sample rates that were less than those supported by 100Mb Ethernet and PC processing. The original version allowed use of UDP and directly following the input stream.  At 10MSPS the Ethernet and PC do not keep up so a switch to using TCP with collecting coherent snap shots was implemented. Both approaches have their merits depending on what you are trying to do with the data and testing. (source code is the "ADC" sub application under the Other directory here )

The following results are from the PC ADC utility that takes a snapshot of coherent data samples, does an FFT with windowing, and averages the results.  All results are in db full scale (dBFS).  All of the results include a history envelope in green which captures the maximum and minimum excursions measured.

Noise Floor

Once the software was updated, the first step was to check for board level noise sources.  The following is a spectra capture with the input tied to ground via a 50 ohm resistor.
ADC at 10MSPS with 50 ohm resistor to ground at input.
While the ADC has differential inputs and better common mode noise immunity I was a little concerned about using the op amp as a single ended to differential conversion with gain (specifically, picking up noise from the BBB).  Fortunately,  there are no surprises here.  Things are nice low and flat across the band.  The average noise floor is a little higher than the vendor datasheet (about 14dB for the same size FFT), however, I expected this somewhat since I have a +20dB amplifier before the ADC and the reference results use a transformer input.

SFDR

The next step was to measure spurious free dynamic range. The largest challenge in this kind of measurement is getting the source harmonics at the input lower than the harmonic levels you are looking to measure at the ADC.  To do this I used a DDS with a 2x cascaded 10.7MHz ceramic filter with a 3dB pad between them to avoid coupling.

This ends up being more complicated than originally expected for a couple of reasons.  First the filter responses at harmonics are not provided by the manufacturer.  The response curve only goes out a few MHz from the filter center.  My understanding is that depending on construction techniques some ceramic filters are susceptible to reduced harmonic rejection due to the mechanical properties of the filter.  If you just assume the harmonic rejection is as good as the stated close in stop band you would expect 70dB of rejection in a 2x cascade.  The DDS produces harmonics that are 20-30dBc.  Taken together we hope to get -90dBc harmonics at the ADC input.

Better than hoping would be to measure.   Unfortunately this is where the harmonic spurious response of the spectrum analyzer comes in.  While measuring the harmonic levels, the fundamental is kept within the passband of the filter and at a high level to bring the harmonics up to a detectable level.  This produces a harmonic response within the test equipment which you cannot differentiate from the harmonics from the device under test.  In conducting this kind of measurement I get harmonics of -60dBc or lower.  A better approach would be to use high pass or notch filters after the device under test to reduce the overall levels into the spectrum analyzer.  The point of this all being that the source harmonic content is someplace between -60 and -90 dBc.

The LTC6406 datasheet shows a second order SFDR of  at least -90dBc.  The LTC2225 datasheet indicates a SFDR of -76 to -90dBc.  The source is the weak spot with a 2nd harmonic of -60 to -90 dBc.

Once the input signal and harmonics were understood better, the next step was the DDS spurs.  I selected frequencies of 10.640MHz and 10.800MHz for evaluation as the spurs at these frequencies were far enough from the fundamental to be caught in the stop band of the filters.  In between these frequencies the spurs varied from 100kHz to 200kHz from the fundamental and landed within the passband of the filter.

The following is a capture of a 10.640MHz filtered input.
10MSPS LTC2225 with LTC6406 Av=10 amplifier capture at 10.640MHz.  Note: only marker #4 is a harmonic, the others are DDS spurs.
At 10MSPS the 10.640MHz signal and harmonics show up at 0.640MHz, 1.28MHz, 1.92MHz, and 2.56MHz.  The only harmonic visible is the second at marker #4 at -87dBFS (This does a fair amount of bouncing and is often not visible, the capture was taken at a peak).  The third harmonic which has an even higher level at the board input is not even observable.  The other signals in the plot are DDS spurs. The fundamental is at marker #1 at -13dBFS.   Based on this we get a 87-13= -74dB SFDR.  

As a sanity check, 10.800MHz was checked.  That spectra is shown below.  


10MSPS LTC2225 with LTC6406 Av=10 amplifier capture at 10.800MHz.  Note only marker#6, 7, and 5 are DDS spurs.
Here the signal and harmonics are at 0.800, 1.6, 2.4, 3.2, 4.0, and 4.8MHz. Unlike 10.640MHz, only markers 5,6, and 7 are clearly DDS spurs whereas the rest correspond to 10.800MHz harmonics.  Just focusing on marker#2 at -87dBFS and the fundamental at -16dBFS we get a differences of 71dB.  This is close to the the results at 10.640MHz and considered within my measurement uncertainty relative to part specifications.  It is interesting to note that the third harmonic is not visible while fourth, fifth and sixth are visible and only slightly less that the second.

Just for grins, I decided to scan the filter envelope with the ADC.  The ADC has much better resolution in frequency and level than any of my test equipment so once you can believe the results its a useful setup.  The following is a 10kHz step scan across the filter using an FFT size that yeilds a bin size roughly equal to the step size.  The markers were manually chosen to follow the envelope.
Filter scan using the ADC.
With this setup I'm within the region of evaluating source/filter harmonics versus internally generated within the amplifier or ADC.  The next logical step would be to correct the PCB to allow using true full scale and use a better source and filter set. So without spending alot of time and energy on better sources and filters I'm going to stop here and call it 70dB or better of SFDR.

2 comments:

  1. I was thinking about trying something like this for a QPSK reciever with a data rate of 460.8Kbps, doing processing onboard.
    With your experience, do you think that this is possible??

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    Replies
    1. Sean,
      Based on measurements and a rough understanding of the digital steps needed, I’m not sure this would work well. The PRUs can sample the data and move it around at 10MSPS but if you try to conduct much calculation on the samples you run out of cycles at their 200MHz clock rate. I have used a 1MSPS stream with some processing on the ARM processor successfully but for QPSK demodulation I think you’ll need more than Nyquist sampling to get a decent bit error rate. This is assuming most or all of the processing is done on the ARM.
      Having said this, you may be able to do some clever things with the first PRU by digitizing and thresholding in the first stage to produce a bit stream of greater than/less than 0 (or some other threshold like quarter scale) in bits which could be handed off to the second PRU for transfer to DRAM. This would reduce your effective transfer rate by 4x - 16x and allow more processing on the second PRU.
      This would be an interesting experiment. I would start by using a test ADC sample set in SRAM on one PRU and then develop test software to treat those samples as ADC reads, threshold and example software on the other PRU. You could then evaluate algorithms, thresholds and bit errors pretty quickly before committing to a board and final sample rates. (a starting framework for this kind of test could be the pru images and ARM code in http://kd2boa.blogspot.com/2014/09/bbb-pru-and-arm-throughput-measurements.html )

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