With a better understanding of the noise floor and spurs on the
ADC board I wanted to check the actual gain produced by the buffer amplifier.
The gain was measured by Tee’ing a DDS output, post filter, to the oscilloscope (with 1M impedance), and into the ADC. The DDS attenuation was varied to produce different levels that were measured on the scope and with the ADC in dBFS and counts. The value of using counts is that the dbFS has small deviations from expected (0.9dB). I believe this is due to an error in my windowing amplitude correction. The ADC count levels are obtained using the peak picking on the time series with the offset found by “peaks” on a noinput signal. The values are all 16 bit normalized. The full scale is 1V. The following table captures measured values and those values processed to produce a voltage gain.

ADC values with input using Rf=294,Rg=25 ohms. 
I trust the large value oscilloscope readings more than the smaller ones (scale had to change and I'm not completely sure of the calibration across scales). Using the ADC count reading the voltage gain is roughly 5.3 (14.5dB). The expected gain is 294/25=11.8 (21.4dB), however, this is fully differential gain on a differential input. The actual and measured input is only half of a differential signal so in this configuration we would expect the single ended input gain to be half or 5.9 (15.4dB, or 6dB lower). To me this agrees well and is fine for my purposes, however, my intuition and mental calculations with differential signals is not what it should be. I often apply the wrong factor (multiply by 2 when the quantity should have been divided by 2 or the other way around). Just for sanity, I decided to use SPICE to verify the setup. Normally I use TINA Spice, however, I had difficulty integrating the LT supplied subckt model (OTA nodes weren't transcribing well). After a brief learning curve I had the circuit below working in LTSpice.

ADC board FDA Spice Model 
The application notes from TI and ADI do a good job of walking through the gain calculation and input impedance. The short summary of that is that the differential feedback network increases the input impedance of the Rg (R7) resistor. By using 25 ohms, the final input impedance is close to (but not exact) 50 ohms and matched with the source. We want the feedback in both paths to see a load impedance that is the same. The combined impedance a the input or top leg is 25 (Rg) +50 (Rsrc) ohms so the resistor on the bottom path is set to 75 ohms.
The following is a spice AC Bode plot of the single ended input and output voltages. The single ended input is less than 0dB as it is referenced to the source (pre source output impedance). It is a little less than a 6dB drop so the input impedance of the amplifier is not exactly 50 ohms (which we knew from the calculations but close enough using standard resistor values). The output is +11.5dB from the reference with the difference between input and output being 15.6dB.

SPICE AC Gain.
SEin=4.5dB, SEout=11.6dB, Voltage gain=15.6dB w/ 8 degree phase variance
across the span. 
This simulation is a nice validation of the calculations and final circuit, however, it is still a little off from the measured values and does not include the LPF at the ADC. The following model does that with the corresponding Bode plot of just Voutse/Vinse.

SPICE model with
output LPF and ADC input model. 
The ADC input model is not very sophisticated. I am not clear on how to properly model the sample and hold input while switching (here a simple parallel RC combination is used). The figure below captures the AC analysis. At 10.7MHz the gain is showing 15dB.

Magnitude and Phase
of Voutse/Vinse with LPF and ADC model.

This is still a half dB off but well within my expectations and needs.
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