Friday, March 11, 2016

Prj 145 - Beagle Bone Black Simple LX9 FPGA board (Part 1)

One of my objectives is still to have a simple and low cost FPGA board to use with an ADC or DAC of intermediate sampling rate (10MSPS – 60MSPS).  There are a number of good off the shelf FPGA boards available to support this (for instance).  After looking at several I kept coming back to the concern that the I/O configuration was just a little less than optimal for what I wanted to do.  For me, I only need one or two FPGA boards, while I pay per square inch for each analog board.  If the headers are wide and offset, then it takes another 3x2 inches I do not really need just to mate the analog and FPGA board.  This then ends up costing 6sq. inches x $5/sq. inch for each analog design in dead area. Said differently, if I could just get the I/O in a slightly different configuration… (this appears to be a costly and slippery slope akin to telling yourself that your current house would be just fine if you only had one more room).

Given the IO desire and a better understanding of what could fit in a Spartan6 LX9 along with what I did and did not require for additional hardware, I decided to try a minimalist hand solderable FPGA board.  The LX9 is the largest part available in a TQG-144, beyond that its BGAs.  To keep things simple all of the IO is 3.3V with a minimal set.  There are 32 pins with a ground every 4 pins in a single header at one edge of the board.  A  SPI and JTAG boundary scan ports are at the other edge of the board.  This configuration allows the mounting on a BeagleBoneBlack and keeping analog daughter card growth at one end of the board.

Notional Board Stack Up of BBB, FPGA Board, and Mixed Signal Board.
Since there are plenty of IO pins (and in an accessible spot) there is also room to add 2 ports of 6 pin GPIO at the end of the board.  These would match the pin-out used in previous I board peripherals and include a +5V supply.  A few additional BBB GPIOs are needed to address the LX9 reset and control pins (DONE, INIT, PROGRAM_B).  A block diagram of the interface configuration is shown below.
BeagleBoneBlack-FPGA Board Interface
One of the key points is that the SPI interface is on BBB pins which are accessible via PRU0.  This is important since the PRUs can be used to obtain higher performance SPI interfaces than the built in hardware units (examples herehere, and here).  While the basic SPI is 4 pins (SCLK, SS, MISO, MOSI) an additional 2 pins were dedicated to provide a 2x SPI (i.e. MISO0, MISO1, MOSI0, MOSI1). I would dedicate more, however, there are virtually no more easily accessible PRU mappable GPIO pins available on P9.  P8 could be used, however, P9 has the +5V from the main power so this would require pins (and obstructions) on both ends of the FPGA board and subsequently the stacked mixed signal board.

Related:
Prj 145 - Beagle Bone Black Simple LX9 FPGA board (Part 1)
Prj 145 - BBB LX9 FPGA Board Design (Part 2)
Prj 145 - BBB LX9 FPGA Board Construction (Part 3)
Prj 145 - BBB LX9 JTAG Boundary Scan Utilities (Part 4)
Prj 145 - BBB LX9 C++ and VHDL (Part5)

Prj 141 - Spartan6 LX9, ADC, and BBB (Part1)

3 comments:

  1. Great project! Is the board shared on OSH Park or GitHub? thanks, drew

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  2. Yes, the KiCad files are available at:
    https://github.com/drone32768/BREC/tree/master/BREC_3/Boards/Fboard

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  3. The OSH Park project is also shared at:
    https://oshpark.com/profiles/KD2BOA

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