Prj137 Fully Differential Amplifier Gain

With a better understanding of the noise floor and spurs on the ADC board I wanted to check the actual gain produced by the buffer amplifier.

The gain was measured by Tee’ing a DDS output, post filter, to the oscilloscope (with 1M impedance), and into the ADC.  The DDS attenuation was varied to produce different levels that were measured on the scope and with the ADC in dBFS and counts.  The value of using counts is that the dbFS has small deviations from expected (0.9dB).  I believe this is due to an error in my windowing amplitude correction.  The ADC count levels are obtained using the peak picking on the time series with the offset found by “peaks” on a no-input signal.  The values are all 16 bit normalized.  The full scale is 1V. The following table captures measured values and those values processed to produce a voltage gain.

ADC values with input using Rf=294,Rg=25 ohms.

I trust the large value oscilloscope readings more than the smaller ones (scale had to change and I'm not completely sure of the calibration across scales).  Using the ADC count reading the voltage gain is roughly 5.3 (14.5dB).  The expected gain is 294/25=11.8 (21.4dB), however, this is fully differential gain on a differential input.  The actual and measured input is only half of a differential signal so in this configuration we would expect the single ended input gain to be half or 5.9 (15.4dB, or 6dB lower).  To me this agrees well and is fine for my purposes, however, my intuition and mental calculations with differential signals is not what it should be.  I often apply the wrong factor (multiply by 2 when the quantity should have been divided by 2 or the other way around). Just for sanity, I decided to use SPICE to verify the setup.  Normally I use TINA Spice, however, I had difficulty integrating the LT supplied subckt model (OTA nodes weren't transcribing well). After a brief learning curve I had the circuit below working in LTSpice.

ADC board FDA Spice Model

The application notes from TI and ADI do a good job of walking through the gain calculation and input impedance.  The short summary of that is that the differential feedback network increases the input impedance of the Rg (R7) resistor.  By using 25 ohms, the final input impedance is close to (but not exact) 50 ohms and matched with the source.  We want the feedback in both paths to see a load impedance that is the same.  The combined impedance a the input or top leg is 25 (Rg) +50 (Rsrc) ohms so the resistor on the bottom path is set to 75 ohms.

The following is a spice AC Bode plot of the single ended input and output voltages.  The single ended input is less than 0dB as it is referenced to the source (pre source output impedance).  It is a little less than a 6dB drop so the input impedance of the amplifier is not exactly 50 ohms (which we knew from the calculations but close enough using standard resistor values).  The output is +11.5dB from the reference with the difference between input and output being 15.6dB.

SPICE AC Gain. SEin=-4.5dB, SEout=11.6dB, Voltage gain=15.6dB w/ 8 degree phase variance across the span.

This simulation is a nice validation of the calculations and final circuit, however, it is still a little off from the measured values and does not include the LPF at the ADC.  The following model does that with the corresponding Bode plot of just Vout-se/Vin-se.

SPICE model with output LPF and ADC input model.

The ADC input model is not very sophisticated. I am not clear on how to properly model the sample and hold input while switching (here a simple parallel RC combination is used). The figure below captures the AC analysis. At 10.7MHz the gain is showing 15dB.

Magnitude and Phase of Vout-se/Vin-se with LPF and ADC model.

This is still a half dB off but well within my expectations and needs.

Source Code Migrated to GitHub

The source code has moved to GitHub at https://github.com/drone32768/BREC

Prj137 BBB and ADC Spurs

While the overall noise floor of the updated ADC was quite good, a couple of low level spurs were present that I wanted to understand.  These show up at 2.004699MHz and 2x (~4MHz) on the particular unit under test.  After unrolling the spurs and taking measurements at a couple of different sampling frequencies they began to really look like 2 and 4MHz, not some higher frequency.  On a quick review of the data sheets for the parts on the board and BBB the first candidate was the BBB primary regulator (TPS65217C). This includes a switching regulator operating at 1.95MHz to 2.55MHz (nominally 2.25MHz).

In a quick attempt, a 10uF bypass capacitor was added across C106 on the SYS_5V supply.  This did make a few dB of improvement in the spurs so I thought I was on the right track. Another 10nF shunt capacitor was added on C119 but to no additional help.

Just to get myself calibrated, the first spur is on the order of -93dBFS which translates into 22uV RMS.  The ADP150 datasheet shows a power supply rejection ratio (PSSR) of -35dB to -40dB for 2MHz and 4MHz.  The amplifier datasheet quotes at least 55dB of PSSR.  The ADC does not quote a PSSR but one would expect at least 20dB - 60 dB.  The board has separate analog and digital power which are decoupled with a SMT choke.  Given all of this I expected to be able to see the source of noise of the board using just a simple scope probe.  On poking around on the board both digital, analog, and supply input - no luck, nothing even close.

In an attempt to do better than a simple oscilloscope probe, a white wire from SYS_5V pin was brought out to a 10uF on a spare SMT pad on the board.  This was then jumpered to an SMA connect which was then attached to a spectrum analyzer.  A picture of that setup is below.

SYS_5V spurious measurement

Low frequency scans were taken with the BBB off and with it on and the ADC operating for comparison.  Those results are below.

Low frequency spectrum with BBB powered off and with it on and ADC operating.

The really low frequency response of the SA used may not be so great (only quoted down to 1MHz), however, the spurs at 2MHz and 4MHz are clear.  The rest of the spectrum up to 100MHz was investigated as well (just to make sure that the source really wasn't a higher frequency and rolling into the low end).  The spectrum was clear (other than the 10MHz ADC sample clock harmonics) while the ADC was operating.

The 2MHz spur at -65dBm above corresponds to roughly 126uV RMS while the -93dBFS from the ADC spectrum corresponds to 22uV.  126/22 = 5.7 which translates to -15dB of attenuation. The bottom line being there is not a whole lot of PSSR compared to what one would expect.

Just to make sure I wasn't doing something silly like pushing the regulator too hard and causing problems I decided to revisit the current consumption budget on the board re-checking the dynamic component.  The following table captures that.

ADC Board Current Consumption

Even factoring in the current from digital and clock IO and using a full swing signal from the amplifier (which this measurement does not have), the current draw on the regulator is a little over half its rating.  Even if the digital line load capacitance is twice what this assumes, the current load would be two thirds the rated 150mA.

With the above in hand, I went back to the board to evaluate the spectrum at different points on the supply using the same setup as above.  The following graph compares the spectrum at the 5V source, 3.3V on-board regulator output and the 3.3V regulated output after the supply choke into the analog section.

Low frequency spectrum of supply line at various points on the ADC board.

No surprises here at the 2MHz noise.  The 4MHz is interesting in that sometimes the noise is pronounced but generally quite low and not noticable on this measurement.  (The envelope history of the analyzer is used so it depends on how long you observe it for and what you are doing - a "shutdown -h now" always creates a period of 4MHz activity).

At this point it seemed that the noise was more subtle than just supply ripple.  With that idea I revisited ground loops (where you won't directly see the currents only the artifacts afterwards and points at which you cannot access for measurement).  The ADI MT-031 application note does a good job going through the various aspects of mixed signal grounding in different environments. With this I realized I did exactly the wrong thing by isolating the analog ground plane with a choke. This would have been ok if I had directly tied the two together at the ADC (as one of the examples in the paper shows).  Fortunately, this was easily addressed by removing the choke (L101) and jumpering across the exposed ground plane edges near the ADC.  The spectrum below was taken with that configuration.

50 ohm grounded input with jumpered grounds

The spurs at 2MHz and 4MHz have dropped about 3dB relative to the choke coupled ground and are now at -100dBFS (marker 3) and -95dBFS (marker 1).

So in the end, the noise environment on the ADC ok.  Even factoring in recommended PCB layout techniques and best practices with ADCs (at least as best as I could do with the tradeoffs presented in a 2" x 3" two layer PCB) there are still switching related spurs.

Prj137 ADC Noise Floor

The first step with the updated ADC is to revisit the noise floor.  To understand just the ADC contribution the zero ohm elements at L106/L103 were removed.  This leaves the ADC inputs open with a 75pF (C115) across them with the 5ohm series inputs which roughly acts as a grounded input. The following is the 10MSPS spectrum.

ADC approximate grounded input spectrum at 10MSPS

The source of the spurs near 2MHz and 4MHz is not clear and will have to wait for another day. The real point of interest is the noise floor at -108dBFS (marker 9 in the above graph). This is in line with the vendor data sheet which shows -110dBFS by my reading of the graphs. There are a few dB of ambiguity due to the width of the noise and using different FFTs and averaging.  I am comparing mid points of the estimated noise band.  Those datasets are also using the 2V range with a transformer while this configuration is using the 1V range.  The datasheet indicates this will "degrade the SNR by 3.8dB". The details of this are not evident to me but I'll go with it.  This would then put the results on par with the datasheet.

The next step is to add the amplifier and ground its input with a 50 ohm SMA terminator. The only filtering present is the shunt 75pF capacitor at C115.  That spectrum is below.

Prj137 50 ohm grounded input.  Amplifier with ADC noise floor at 10MSPS.

Again, marker 9 is at the estimated noise floor and is showing a noise floor of -107dBFS. This is actually better than I expected.  The buffer amplifier is adding very little noise. The gain setting for this configuration is Rg=25 ohms / Rf=294 ohms or Av=11.7 which is more than many buffers of 1 or 2.

Finally, a histogram was taken of the grounded input configuration. Looking at the frequency spectrum and time series provides a lot of useful information in tracking down problems but I have also come to appreciate the value of a histogram.  The initial efforts with this board over looked a software work around from the previous board where some of the LSB were incorrectly masked.  This was not at all obvious in the grounded input time series or spectrum but was very clear in the histogram.  The following is the histogram of the 50 ohm terminated board input with amplifier (same as previous spectrum).

The VCOM bias point sits right between codes 2053 and 2054 and is only a mV or so from nominal value at 2048.  All other bins not shown were verified to be zero.

As points of reference, the LSB is 1V / 2^12 = 1/4096 = 244uV.  For noise evaluation using the processing gain of the FFT the -90 dBFS RMS voltage is dBFS = 20 * log10(Vnoise / 0.5V) or Vnoise = 0.5V * 10^( -90 dBFS / 20 ) = 16uV.

Prj137 10MSPS ADC

A couple of updates to the ADC board were made.  These included corrections to the power on reset circuitry and the addition of 0805 pads for a band pass filter between the buffer and the ADC.  The schematic is below.

10MSPS ADC Cape for Beaglebone Black

Walking through the schematic, the regulator and power on reset circuitry are in the upper right. A low noise regulator is used to provide 3.3V within the board.  The output enable of the ADC is generated by and'ing together the BBB system reset line with a gpio line.  The gpio used was selected as it powers up low and must be explicitly set high.  The outputs of the ADC must remain in a high Z state as they are on the boot config pins of the BBB.  If you don't do this, they are loaded by the ADC and the unit does not boot correctly.

The clock circuitry is immediately below this.  A simple CMOS TCXO is used, however, provisions are made for a divide by two configuration.  The land is chosen for a FOX924B.  This part has worked well for me in the past and is widely available in frequencies from 10MHz to 27MHz.  While the ADC is capable of 10MSPS the divide by two allows for various sample clock frequencies to be used.  For example a 19.44MHz TCXO can be used with a divide by 2 to produce a sample clock of 9.72MHz.  This sample frequency has the advantage that is shifts the location of 10.7MHz closer to the center of a Nyquist band than just using a 10.0MHz sample clock.

The LTC2225 in the lower left connects to 12 bits on the PRU1 input register.  In addition, the sample clock is present as an input.  This allows the PRU to wait for a sample clock transition and then read the ADC value.  The ADC is strapped to produced unsigned integer values and the range is set for 1V.  The common output voltage is bypassed with a capacitor and provided to the buffer amplifier.

Immediately above the ADC in the schematic is a filter network between the buffer amplifier and the ADC.  This can be populated in a variety of configurations from a 3rd order bandpass filter to a simple first order low pass filter.  In its simplest configuration all of the series elements are 0 ohm pass throughs and none of the shunt elements are populated except C115 (75pF).  This configuration provides a first order 21MHz low pass filter (the 3dB point is chosen to be at the second harmonic).

The LTC6404 is in the upper left and provides buffering, amplification, and single ended to balanced conversion.  The QFN version of the device is used so there are integrated 50 ohm resistors in line with each output.  These work with the filter network following it.  The LTC6406 provides both single ended to balanced conversion and some gain.  Using a fully differential amplifier (FDA) has some of subtleties. There are good application notes on FDAs from both TI and ADI.  The resistor values are correct as it is designed to be a 50 ohm input with a 50 ohm source.  The 25 ohm resistor R102 appears as roughly 50 ohms input impedance with the feedback network of the FDA.  The other side input of the FDA output sees both the 25 ohm gain resistor plus 50 ohms to balance out the source impedance, thus producing 75 ohms and balancing both sides of the amplifier.

The io pins are chosen to allow an interface board to be stacked on top without interfering.  This allows a couple of ports of SPI/GPIO and power to 3 other boards from the same BBB hosting the ADC.  The ground plane is separated into a digital and analog plane with the analog plane surrounding the buffer amplifier, filter, and ADC input.  This plane is tied to the rest of ground at a single point through ferrite chokes.  The 3.3V supply is also separated into an analog and digital portion via a choke.  A view of the PCB is at the end of the BREC2 Gallery. The sample clock runs are not as nice as I would like but there is only so much you can do with two layers.

A picture of the first unit is below.

10MSPS ADC on a Beaglebone Black.  TCXO in upper left, LTC2225 in upper right, power on reset and regulators lower left and LTC6406 in lower right.

This approach is still low cost and can be easily constructed by hand. The populated board is roughly $45 (LTC6406 $7, LTC2225 $10 FOX924 $3 ADP150 $1 - all quantity 1 from Digikey, connectors $5 from Adafruit, SMA $1 from eBay quantity 25 and PCB $11 quantity 3 from OSHPark).

Level Controlled RF CW Synthesizer

Using an amplifier, attenuator, splitter and power detector (Prj135) along with an older project with an ADF4351 synthesizer (Prj131 - a variant of Prj133 without the mixer), a Beagle Bone Black, and a SPI interface (Prj130), a controlled level RF CW synthesizer configuration was created.  Without some kind of feedback a standalone signal source is susceptible to level variance, particularly with load reactance and interaction with cable length - an example is here.  By measuring and attenuating you get an AGC loop to set the level.  A block diagram of the setup is below.

Block Diagram of Constant Level Synthesizer Setup using a Beaglebone Black.

A picture of the physical setup is below.

Level Controlled Synthesizer Setup.  Beaglebone Black at left with interface board, synthesizer in upper center, and level control board on right.

The synthesizer has a coarse level control (3 steps of approximately 3dBm).  The digital step attenuator provides 30dBm of attenuation while the amplifier +20dB of gain up to +8dBm through 2700MHz. Software on the Beagle Bone Black sets the synthesizer at its lowest output level at the desired frequency along with maximum attenuation at the digital attenuator.  The power at the detector is measured (multiple samples averaged over 5mS) and compared to the desired level.  The attenuation is reduced by half the delta until the detector reading is within 0.25dBm of the target or until the attenuation setting is 0dB.  If the level cannot be achieved, the synthesizer output level is increased one step and the entire process is repeated.  The following diagram captures measured outputs at various levels and with different measurement devices.

Level Controlled Synthesizer 0.040 - 2 GHz Results

All devices show are +/-2dB. The 0dBm output at 1900MHz shows a sag where the synthesizer output has dropped enough with frequency that the amplifier cannot bring it quite to 0dBm.  You can see the SA0314 has a couple of small spikes in response around 500MHz and 1100MHz. You can also see the 7L12 agrees quite well until about 1500MHz (the traces stop at 1800MHz as this is its limit).

Prj135 RF RMS Power Meter (Part3)

I decided to construct the second level control board using a power divider rather than sampling network to the RMS power detector as in the previous post.  Using a sampling resistor loads the output less but is susceptible to errors based on the load impedance variance. There is a choice between using a two resistor and three resistor configuration.  A detailed treatment of why a 2R divider works better than a 3R divider for level ratio applications is well described in “Choosing the Right Power Splitter: Two-resistor or Three-resistor; B. R. Smith, National Conference of Standards” (Currently available from the Keysight website).  The modifications to the original circuit are shown below.

2R 6dB Power Splitter with Matching Network for LTC5587

A picture of the end result is shown below.  You can see the stacked capacitor over the underlying cut trace between the 50 ohm resistor and the SMA post.  In the lower right you can see the matching network to the power meter.

Unit #2 using a 2R divider (upper right between U103 and SMA) and 50 ohm matching network at meter (lower right to the right of the LTC5587 at U105).

The mV/dBm response of the meter was measured using the same techniques described in the previous post. The following graph shows scans for the sub 1GHz region.

Power Meter Response 40MHz - 1000MHz.

The results are amazingly good and near Y [dBm] = (M=32.5 mV/dBm) * mV + (B=-43 dBm). The measurement error of the instrumentation equipment and setup is at least +/- 2 dBm.  The following is the same data over the 1GHz - 2GHz region.

Power Meter Response 1000MHz - 2000MHz

The results in this band are floating a bit high compared with the previous band but still within measurement error and device specification.  The following captures the response in the 2GHz - 3GHz region.

Power Meter Response 2000MHz - 3000MHz

Again, the results are bit higher than the 1GHz band but within expected results.  The amplifier is only stated to 2700MHz so you see the level reduction starting here.

The slope and intercept are both a little higher than the nominal value from the datasheet.  They actually look closer to some of the higher temperature data listed.  My guess is I didn't get the QFN paddle soldered sufficiently well to make a good thermal junction and the part is running warm.

A couple of different 50 ohm matching configurations were tried. No matching (device direct) worked well in the sub 1GHz region and increased sensitivity, however, above this the results were not usable.  A 2.2nH serial inductor with no shunt capacitor was tried.  This produced good results through 2GHz (not much difference than the above except the >1900MHz results were closer to the B=-43dBm line).