ADC without Amplifier

In an effort to evaluate the ADC harmonic distortion and spur clusters I decided to create a variant of the ADC board which did not have the amplifier (earlier version).  This allows me to revisit the ground plane, add resistors to the digital lines and re-layout the sample clock signal.  It ends up being as close to the ADC reference design as possible.

BeagleBone ADC board with transformer input.

The first unit anti aliasing filter was not populated to allow evaluation at multiple frequencies.  Two different regulators were tried - the original 150mA and a 300mA version.

Constructed ADC board with transformer input and no amplifier. ADC anti-aliasing filter not populated.  TCXO in upper right, input transformer at lower right, ADC right of upper center, regulator and reset on left.

As in previous measurements, a DDS at 10.640MHz was used as the input.  This was filtered through a 2x 10.7MHz ceramic filter.  Without the amplifer this setup was not able to drive full scale, rather -3dBFS.  That spectrum is shown below.

-3dBFS 10.640MHz input

HD2 is still -79dBc and the spur clusters are present at the same levels and locations as the same version of the board with amplifier ( HD2 compare and spur cluster compare).  The grounded input spectrum looked similar to the previous versions with the amplifier (flat at -107dBc with small clusters at 2MHz and 4MHz in the -100dBFS range).

The continued presence of the spur clusters is disappointing but I am out of ideas on the root cause and decided to put it away for a while and move on to other topics.

Prj137 ADC Spur Clusters

The spur clusters from the previous work proved to be an evasive problem.  Very little changes the location or the level. The structure seems to indicate there are many harmonics present based on the clustering.  To better understand this I walked the source up and down to see which ways the clusters moved (i.e. in even or odd nyquist intervals).  A capture of that is below.

Spur cluster walk from 10.640MHz up in steps of a few kHz.

Using the even/odd interval, I then stepped the fundamental by a few kHz for several steps and captured the peak of each cluster.  A fundamental delta of 10kHz moves the clusters 10kHz, not some multiple.  This told me I was looking at a modulation, not a set of harmonics of something.  If you put all of this into a spreadsheet and play around ruling out things based on even/odd nyquist and unrolling a given peak to all of the frequencies it could be you get the following table.

Spur cluster peak unrolling across Nyquist intervals

The cluster peaks are under "ADC (MHz)" and the color codings of cells match up the expected frequency the cluster represents after folding.  The rows at the bottom capture the delta in MHz of the peak from the fundamental at 10.640MHz.  So for the highest peaks of the spur clusters they appear to be 2MHz from the fundamental and appear to me to be switching power supply noise, evaluated here.  The lower spurs within the cluster would then be the AM modulated signals of the higher harmonics of the 2MHz switching impulses folded around the Nyquist regions.

Indeed, you can do the same thing at a lower sampling rate.  This both shows the fine scale structure and the harmonic spurs and verifies the above unrolling at a different set of frequencies. The following is a 2.5MSPS capture of a 10.640MHz input signal.

10.640MHz input signal using 2.5MSPS showing the spur cluster internal structure.

Numerous attempts were made to ameliorate the clusters.  This included adding/changing the supply chokes and bypass coupling.  As previously, these made no impact.  Additional ground ties were added, and removed - again with no impact.  The next logical step (in my mind) is to understand if these are coming from the amplifier or the ADC and to remove as much of the circuitry as possible.  This means backing up to a just the ADC and a transformer input - basically mirroring the ADC evaluation unit circuit.

Prj137 Onboard BPF

Given the state of HD2 from the previous post with the BBB 10MSPS ADC board, I used Elsie to design a 3rd order BPF centered at 10.7MHz with a 3.5MHz bandwidth.  It takes a bit of trial and error to arrive at a synthesizable filter (i.e. one that uses standard values and is not overly sensitive to part value variations).  The intent is not to provide complete band rejection, rather to limit the noise from folded Nyquist bands and to knock down any harmonics created by the FDA.  The filter values along with a spice run are shown below.

SPICE steup of FDA with BPF prior to ADC.

The 902pF shunt capacitor is an 820pF with a 82pF stacked on top (the target was 900pF however these were unavailable at reasonable prices and shipping times).

BPF Filter Response

For comparison purpose the first spectrum below is the same measurement setup with no filter.  In this case (and all following) the gain has been reduced using an Rf=100, Rg=25 (this was one of the attempts to see if gain was exacerbating the harmonic distortion).

Av=4, Filtered DDS source at 10.640Mhz, no FDA-ADC filtering.

Rather than just populating the entire filter and seeing what happened, I decided to populate each stage and evaluate HD2/HD3 and the noise floor.  I chose to evaluate the center shunt stage first since I thought this had the best chance of producing expected results without imbalancing the differential arms.  Those results are below.

Av=4, Filtered DDS source at 10.640MHz with shunt stage of FDA-ADC BPF populate.

At first it seems worse, however, the noise floor has been reduced by the BPF limiting the folding noise across Nyquist zones.  This presents the illusion of the spurs being more prominent not because they have risen but because the floor as dropped.  HD2 is now roughly -74dBc and HD3 is not noticeable.  I did not pause to measure the gain and evaluate the filter insertion loss.  If one stage was good more must be better...  Unfortunately, this wasn't true.  Adding the first series made things slightly worse and with a higher noise floor.  Adding the second series stage and final BPF stage helped HD2 slightly but retained a slightly higher and tilted noise floor.  Addition of the final LPF (shunt C and series 5 ohm resistors) returned things to slightly better than the above.  The results from this configuration are shown below.

Av=4, Filtered DDS source at 10.640 MHz with 3 stage BPF.

HD2 is now approximately -80dBc but HD3 is similar but a little higher.  Interestingly enough, in no case did the spur clusters ever change.  These are now the dominant (and unexplained) feature.

At this point it was time to total up the bill for all of the filtering.  I knew the insertion loss was creeping up since the DDS level had to be adjust up to hit nearly full scale on the ADC.  I decided to return the FDA to a high gain previously used Rf=493 and evaluate the results.

Rg=25, Rf=493, Filtered DDS source at 10.640MHz with 3 stage BPF.

As expected the spectrum did not change with the increased gain. Using the same technique as in previous gain measurements, the gain was measured as Av=15.6(15dB) but Rg/Rf indicated it should be Av=9.9(20dB).  The FDA datasheet indicates this type of gain is readily supported by the device at this frequency so it looks like the insertion loss is 5dB for the 3rd order BPF.  This is higher than I had hoped for, however, I did not use the highest Q components made, rather the best ones in stock for these values at the time.

So in the end it appears the higher than expected HD2/HD3 response is predominantly deriving from the FDA and how it is being used.  Taking them down to a reasonable level adds components and increased gain needs on the FDA.  This seems like a losing game.  I may have been better off placing all of the desired gain off board, then filtering, and then conducting the differential conversion on the board with a transformer.

This is still usable for my purposes, however, the spur clusters merit some attention.  Originally I had attributed them to DDS artifacts, however, it became clear this was not the case when using a source comprised of a synthesizer and mixer.  In both cases the spurs are identical in level and structure and follow the fundamental in frequency and level.

Prj137 HD2

Continuing with the ADC and having data on the noise floor and amplifier gain, the next step is to revisit the harmonic distortion of the board.  Previous efforts on earlier boards left me with questions regarding how much of the second harmonic (HD2) response observed was from the device versus the source and filters. When measuring a strong signal it is difficult to assess the harmonic content since even good spectrum analyzers will have a harmonic response themselves larger than I am trying to investigate with a 12 bit ADC.  The basic test filter I use is a 2x cascaded 10.7 MHz ceramic with a 3dB pad between them and a LC match from 50 ohms to 330 ohms.  The vendor does not provide a broadband filter response so I have always been left wondering what the actual response is at the harmonics (best case 50dB of rejection, worst case ...).  To address this I decided to construct a notch filter and focus only on HD2.

Below is the filter schematic and spice simulation.  I used the Elsie software package and selected L/C values I had on hand for a 50 ohm termination and notch response at HD2 for a 10.7MHz signal.

Notch Filter for Approximately 21.4Hz (HD2 of 10.7MHz signal)

The filter was constructed on some scrap PCB using an Xacto knife to cut the pads.  It is a bit tedious and care must be taken to do this away from other boards to avoid copper shavings landing where you don't want them but for small things it is faster than waiting for a board.

Constructed HD2 Notch Filter

The response of the filter was measured with a spectrum analyzer set at an input level of -15dBm. The response was scanned in large increments to save time hence the steps in the response.

Measured Response of Filter

The rejection in the range of interest is -50 to -70 dB and I trust the results in measuring the notch response more than than the harmonic response since the total input signal level is low causing less uncertainty regarding the measurement device behavior.

Using the above notch filter and a 10.7MHz BPF and ADC Unit#1 the following spectra was obtained with a synthesizer/mixer source (non-DDS).

ADC measurement of 10.640 MHz input through notch filter and BPF.

Unfortunately, HD2 is only ~65dBc.  This is significantly less than expected.  In addition there are several spur clusters besides HD2 and HD3 (markers 3,4,5,6). In fact, this is worse than the 74dBc from an earlier version of the board at lower levels.  With this measurement, there is no question regarding the input level of HD2; the notch should provide in excess of 50dB of HD2 rejection, the source HD2 is measured at least -40dBc, and the ceramic filter should provide another 25-50dB of HD2 reduction.

My first estimate was that the distortion was occuring in the fully differential amplifier (FDA). The datasheet shows -80dBc to -90dBc for HD2 and HD3 under various feedback configurations and loads at 10MHz using a 2Vpp output and a single ended input. There is a figure showing 10dB of variation in this with different common mode voltages (near the range I am operating using the ADC common mode voltage output).

In an effort to probe the FDA contribution, I changed the gain of the FDA down and up (ensuring all resistors were 1%).  In no case did this change HD2, HD3 or the spur clusters levels.

The last aspect of this which I can think of is that my input resistor is small compared to general applications referenced in the datasheet.  The exact impacts of this on distortion are not clear to me (if any).

In the update of the board, a BPF filter was added between the ADC and FDA just for this concern. The next step is to leverage the filter and monitor response changes in HD2/HD3 and the spur clusters with the idea being if they are attenuated the FDA is the source, if not, the ADC is the prime contributor.

Prj137 Fully Differential Amplifier Gain

With a better understanding of the noise floor and spurs on the ADC board I wanted to check the actual gain produced by the buffer amplifier.

The gain was measured by Tee’ing a DDS output, post filter, to the oscilloscope (with 1M impedance), and into the ADC.  The DDS attenuation was varied to produce different levels that were measured on the scope and with the ADC in dBFS and counts.  The value of using counts is that the dbFS has small deviations from expected (0.9dB).  I believe this is due to an error in my windowing amplitude correction.  The ADC count levels are obtained using the peak picking on the time series with the offset found by “peaks” on a no-input signal.  The values are all 16 bit normalized.  The full scale is 1V. The following table captures measured values and those values processed to produce a voltage gain.

ADC values with input using Rf=294,Rg=25 ohms.

I trust the large value oscilloscope readings more than the smaller ones (scale had to change and I'm not completely sure of the calibration across scales).  Using the ADC count reading the voltage gain is roughly 5.3 (14.5dB).  The expected gain is 294/25=11.8 (21.4dB), however, this is fully differential gain on a differential input.  The actual and measured input is only half of a differential signal so in this configuration we would expect the single ended input gain to be half or 5.9 (15.4dB, or 6dB lower).  To me this agrees well and is fine for my purposes, however, my intuition and mental calculations with differential signals is not what it should be.  I often apply the wrong factor (multiply by 2 when the quantity should have been divided by 2 or the other way around). Just for sanity, I decided to use SPICE to verify the setup.  Normally I use TINA Spice, however, I had difficulty integrating the LT supplied subckt model (OTA nodes weren't transcribing well). After a brief learning curve I had the circuit below working in LTSpice.

ADC board FDA Spice Model

The application notes from TI and ADI do a good job of walking through the gain calculation and input impedance.  The short summary of that is that the differential feedback network increases the input impedance of the Rg (R7) resistor.  By using 25 ohms, the final input impedance is close to (but not exact) 50 ohms and matched with the source.  We want the feedback in both paths to see a load impedance that is the same.  The combined impedance a the input or top leg is 25 (Rg) +50 (Rsrc) ohms so the resistor on the bottom path is set to 75 ohms.

The following is a spice AC Bode plot of the single ended input and output voltages.  The single ended input is less than 0dB as it is referenced to the source (pre source output impedance).  It is a little less than a 6dB drop so the input impedance of the amplifier is not exactly 50 ohms (which we knew from the calculations but close enough using standard resistor values).  The output is +11.5dB from the reference with the difference between input and output being 15.6dB.

SPICE AC Gain. SEin=-4.5dB, SEout=11.6dB, Voltage gain=15.6dB w/ 8 degree phase variance across the span.

This simulation is a nice validation of the calculations and final circuit, however, it is still a little off from the measured values and does not include the LPF at the ADC.  The following model does that with the corresponding Bode plot of just Vout-se/Vin-se.

SPICE model with output LPF and ADC input model.

The ADC input model is not very sophisticated. I am not clear on how to properly model the sample and hold input while switching (here a simple parallel RC combination is used). The figure below captures the AC analysis. At 10.7MHz the gain is showing 15dB.

Magnitude and Phase of Vout-se/Vin-se with LPF and ADC model.

This is still a half dB off but well within my expectations and needs.

Source Code Migrated to GitHub

The source code has moved to GitHub at https://github.com/drone32768/BREC

Prj137 BBB and ADC Spurs

While the overall noise floor of the updated ADC was quite good, a couple of low level spurs were present that I wanted to understand.  These show up at 2.004699MHz and 2x (~4MHz) on the particular unit under test.  After unrolling the spurs and taking measurements at a couple of different sampling frequencies they began to really look like 2 and 4MHz, not some higher frequency.  On a quick review of the data sheets for the parts on the board and BBB the first candidate was the BBB primary regulator (TPS65217C). This includes a switching regulator operating at 1.95MHz to 2.55MHz (nominally 2.25MHz).

In a quick attempt, a 10uF bypass capacitor was added across C106 on the SYS_5V supply.  This did make a few dB of improvement in the spurs so I thought I was on the right track. Another 10nF shunt capacitor was added on C119 but to no additional help.

Just to get myself calibrated, the first spur is on the order of -93dBFS which translates into 22uV RMS.  The ADP150 datasheet shows a power supply rejection ratio (PSSR) of -35dB to -40dB for 2MHz and 4MHz.  The amplifier datasheet quotes at least 55dB of PSSR.  The ADC does not quote a PSSR but one would expect at least 20dB - 60 dB.  The board has separate analog and digital power which are decoupled with a SMT choke.  Given all of this I expected to be able to see the source of noise of the board using just a simple scope probe.  On poking around on the board both digital, analog, and supply input - no luck, nothing even close.

In an attempt to do better than a simple oscilloscope probe, a white wire from SYS_5V pin was brought out to a 10uF on a spare SMT pad on the board.  This was then jumpered to an SMA connect which was then attached to a spectrum analyzer.  A picture of that setup is below.

SYS_5V spurious measurement

Low frequency scans were taken with the BBB off and with it on and the ADC operating for comparison.  Those results are below.

Low frequency spectrum with BBB powered off and with it on and ADC operating.

The really low frequency response of the SA used may not be so great (only quoted down to 1MHz), however, the spurs at 2MHz and 4MHz are clear.  The rest of the spectrum up to 100MHz was investigated as well (just to make sure that the source really wasn't a higher frequency and rolling into the low end).  The spectrum was clear (other than the 10MHz ADC sample clock harmonics) while the ADC was operating.

The 2MHz spur at -65dBm above corresponds to roughly 126uV RMS while the -93dBFS from the ADC spectrum corresponds to 22uV.  126/22 = 5.7 which translates to -15dB of attenuation. The bottom line being there is not a whole lot of PSSR compared to what one would expect.

Just to make sure I wasn't doing something silly like pushing the regulator too hard and causing problems I decided to revisit the current consumption budget on the board re-checking the dynamic component.  The following table captures that.

ADC Board Current Consumption

Even factoring in the current from digital and clock IO and using a full swing signal from the amplifier (which this measurement does not have), the current draw on the regulator is a little over half its rating.  Even if the digital line load capacitance is twice what this assumes, the current load would be two thirds the rated 150mA.

With the above in hand, I went back to the board to evaluate the spectrum at different points on the supply using the same setup as above.  The following graph compares the spectrum at the 5V source, 3.3V on-board regulator output and the 3.3V regulated output after the supply choke into the analog section.

Low frequency spectrum of supply line at various points on the ADC board.

No surprises here at the 2MHz noise.  The 4MHz is interesting in that sometimes the noise is pronounced but generally quite low and not noticable on this measurement.  (The envelope history of the analyzer is used so it depends on how long you observe it for and what you are doing - a "shutdown -h now" always creates a period of 4MHz activity).

At this point it seemed that the noise was more subtle than just supply ripple.  With that idea I revisited ground loops (where you won't directly see the currents only the artifacts afterwards and points at which you cannot access for measurement).  The ADI MT-031 application note does a good job going through the various aspects of mixed signal grounding in different environments. With this I realized I did exactly the wrong thing by isolating the analog ground plane with a choke. This would have been ok if I had directly tied the two together at the ADC (as one of the examples in the paper shows).  Fortunately, this was easily addressed by removing the choke (L101) and jumpering across the exposed ground plane edges near the ADC.  The spectrum below was taken with that configuration.

50 ohm grounded input with jumpered grounds

The spurs at 2MHz and 4MHz have dropped about 3dB relative to the choke coupled ground and are now at -100dBFS (marker 3) and -95dBFS (marker 1).

So in the end, the noise environment on the ADC ok.  Even factoring in recommended PCB layout techniques and best practices with ADCs (at least as best as I could do with the tradeoffs presented in a 2" x 3" two layer PCB) there are still switching related spurs.